ITP700 Debug Port Design Guide

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ITP700 Debug Port Design Guide
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* ADDITIONAL REQUIRED SUBCIRCUITS INCLUDED IN ITP700_PACKAGES.TXT:
* QSOP = QSOP PIN MODEL, PACKAGE APPROXIMATION
* MINITEK* = ITP DPA HEADER MODEL
*
* ADDITIONAL MODELS THAT MAY BE ADDED:
* mc100lvel17 = MOTOROLA* ECL RECEIVER
* qs3vh125 = QUALITY SEMICONDUCTOR* QUICKSWITCH
*
***************************************************
*
.SUBCKT FBO GNDREF M2 ECL POW
*THE FOLLOWING SETS UP VREF AS .66 POW NODE
EM1 VREF GNDREF POW GNDREF .66
*
* The following is a generalization of the qs3vh125
* a true spice model of the quickswitch may be
* added between pins M1 and FBOQS.
* Be sure to remove the following
* generalization If the true spice model is used
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* FBO Path through quickswitch
* QSOP Pin Model
X1 M1 INT1 GNDREF QSOP
* Quickswitch Internal Resistance
RQS INT1 INT2 4
* QSOP Pin Model
X2 FBOQS INT2 GNDREF QSOP
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