Intel Xeon Processor Specification Update
Intel
®
Xeon
®
Processor Specification Update 23
Summary Table of Changes
P26 XXXXXXXNo FixThe processor signals page-fault exception (#pf)
instead of alignment check exception (#ac) on an
unlocked cmpxchg8b instruction
P27 XXX FixedIncorrect data may be returned when page tables
are located in write combining (WC) memory
P28 XXXXXXXNo FixFSW may not be completely restored after
page-fault on FRSTOR or FLDENV instructions
P29 XXX FixedWrite combining (WC) load may result in an
unintended address on system bus
P30 XXXXXXXNo FixProcessor provides a 4-byte store unlock after an
8-byte load lock
P31 XXX FixedMultiple accesses to the same S-state L2 cache
line and ECC error combination may result in loss
of cache coherency
P32 XXXXXXXNo FixIA32_MC0_ADDR and IA32_MC0_MISC registers
will contain invalid or stale data following a data,
address, or response parity error
P33 XXXXXXXNo FixWhen the processor is in the system management
mode (SMM), debug registers may be fully
writeable
P34 XXXXXXXNo FixAssociated counting logic must be configured
when using event selection control (ESCR) MSR
P35 XXX FixedLivelock may occur when bus parking is disabled
P36 XXX FixedCR2 May be incorrect or an incorrect page-fault
error code may be pushed on to stack after
execution of an LSS instruction
P37 XX FixedBuffer on resistance may exceed specification
P38 XFixedInstruction pointer stored on stack may become
invalid
P39 XXXXXNo FixShutdown and IERR# may result due to a machine
check exception on a Hyper-threading Technology
enabled processor
P40 XFixedHyper-Threading Technology enabled processors
may hang in the presence of extensive
self-modifying code
P41 XFixedGlobal bit incorrectly set for secondary logical
processors in ITLB
P42 XFixedMachine check exception (MCE) observed on DP
platforms
P43 XXXXXPlan FixBPM[5:3]# VIL does not meet specification
P44 XXXXXNo FixProcessor may hang under certain frequencies and
12.5% STPCLK# duty cycle
P45 XXXXXXXNo FixSystem may hang if a fatal cache error causes bus
write line (BWL) transaction to occur to the same
cache line address as an outstanding bus read line
(BRL) or bus read-invalidate line (BRIL)
P46 XXX FixedL2 cache may contain stale data in the exclusive
state
Errata (Sheet 2 of 4)
No.
C1/
0F0Ah
D0/
0F12h
B0/
0F24h
C1/
0F27h
D1/
0F29h
M0/
0F25h
L0/
0F29h
Plans Errata