Intel Xeon Processor MP Specification Update

32 Intel
®
Xeon
®
Processor MP Specification Update
Errata
Implication: The processor unexpectedly does not flag #GP on a non-zero write to the upper 32 bits of
IA32_CR_SYSENTER_EIP or IA32_CR_SYSENTER_ESP. No known commercially available
operating system has been identified to be affected by this erratum.
Workaround: None at this time.
Status: For the steppings effected, see the Summary Table of Changes.
O42 Counting both L2 and L3 cache reference events may result in undercount
Problem: The processor’s counting logic combines events from misaligned pipestages. Thus, if two requests
are sent referencing L2 and L3 at the same time, the EMON logic may only log them as one event.
Implication: This may result in undercounting of cache reference events.
Workaround: Restrict to counting either L2 or L3 events, but not both at the same time on a single ESCR.
Status: For the steppings effected, see the Summary Table of Changes.
O43 Simultaneous assertion of A20M# and INIT# may result in incorrect data
fetch
Problem: If A20M# and INIT# are simultaneously asserted by software, followed by a data access to the
0xFFFFFXXX memory region, with A20M# still asserted, incorrect data will be accessed. With
A20M# asserted, an access to 0xFFFFFXXX should result in a load from physical address
0xFFEFFXXX. However, in the case of A20M# and INIT# being asserted together, the data load
will actually be from the physical address 0xFFFFFXXX. Code accesses are not affected by this
erratum.
Implication: Processor may fetch incorrect data, resulting in BIOS failure.
Workaround: Deasserting and reasserting A20M# prior to the data access will workaround this erratum.
Status: For the steppings effected, see the Summary Table of Changes.
O44 Incorrect Brand ID and Brand string
Problem: The Brand ID for the production (S-Spec) Intel Xeon processor MP processors should be 0Bh,
which is associated with the Intel-branded text string “Intel(R) Xeon(R) Processor MP”. The Brand
ID returned by all production (S-Spec) Intel Xeon processor MP is 0Eh, which is associated with
the Intel branded text string “Intel(R) Xeon(R) Processor”. In addition the Brand String extensions
to the CPUID instruction also return the incorrect brand string, “Intel(R) Xeon(R) CPU x.sixth”.
Brand ID is a processor identification feature that is accessible via the CPUID instruction.
Processors that implement the Brand ID feature return an 8-bit value in bits 7 through 0 of the EBX
register when the CPUID instruction is executed with EAX=1. A full description of the Brand ID
feature and a table of Brand ID values returned by various processors is included in the Intel®
Processor Identification and the CPUID Instruction (AP-485) Application Note (see
http://developer.intel.com/design/xeon/applnots/241618.htm).
Implication: Intel expects the impact of this issue to be limited to incorrect processor identification on BIOS
POST or OS system information screens. However, BIOS developers and OEM system board
manufacturers should judge the impact of this Brand ID issue on their existing platform designs
incorporating the Intel Xeon processor MP.
Workaround: Refer to the Processor Signature portion of the CPUID instruction when determining processor
brand. A processor signature of 0F11h = Intel(R) Xeon(R) processor MP.
Status: For the steppings effected, see the Summary Table of Changes.
O45 CPUID instruction returns incorrect number of ITLB entries
Problem: When the CPUID instruction is executed with EAX = 2 on a processor without HT Technology or
with HT Technology disabled via power on configuration, it should return a value of 51h in
EAX[15:8] to indicate that the instruction translation lookaside buffer (ITLB) has 128 entries. On a