Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

10 Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide
5-3 BR[3:0]# Connection for DP Configuration ......................................................... 67
5-4 Topology for PWRGOOD (CPUPWRGOOD) ..................................................... 69
5-5 Topology for Asynchronous GTL+ Signals Driven by the Processor .................. 69
5-6 Recommended THERMTRIP# Circuit................................................................. 70
5-7 Topology for Asynchronous GTL+ Signals Driven by the Chipset ...................... 71
5-8 INIT# Routing Topology ...................................................................................... 72
5-9 Voltage Translator Circuit.................................................................................... 72
5-10 Circuit Implementation for Hardware-Based SMBus Selection Using Mux......... 76
5-11 Circuit Implementation for Hardware-Based SMBus Selection Using FET......... 77
5-12 Circuit Implementation for Firmware-Based SMBus Selection ........................... 78
5-13 BSEL[1:0] Reference Circuit ............................................................................... 82
6-1 3-DIMM per-Channel Implementation ................................................................. 84
6-2 4-DIMM per-Channel Implementation ................................................................. 84
6-3 Example of Proper Single and Dual Rank Mixing ...............................................85
6-4 Example of Incorrect Single and Dual Rank Mixing ............................................ 85
6-5 Trace Width and Spacing for All DDR Signals Except
CMDCLK_x[3:0]/CMDCLK_x[3:0]# ..................................................................... 86
6-6 Source Synchronous Topology ........................................................................... 88
6-7 Command Clock Topology.................................................................................. 89
6-8 Trace Width/Spacing for CMDCLK/CMDCLK# Routing...................................... 90
6-9 Source Clocked Signal Topology ........................................................................ 91
6-10 Chip Select Topology .......................................................................................... 92
6-11 CKE Topology ..................................................................................................... 93
6-12 Receive Enable Signal Routing Guidelines......................................................... 95
6-13 DDRCOMP Resistive Compensation .................................................................. 96
6-14 DDRVREF Voltage Regulator ............................................................................. 97
6-15 DDRVREF Voltage Divider ................................................................................. 97
6-16 Routing DDRVREF and ODTCOMP ................................................................... 98
6-17 DDRCVOL, DDRCVOH, and DDRCVO Network................................................ 99
6-18 DDR VTerm Plane ............................................................................................ 100
6-19 DIMM Decoupling.............................................................................................. 101
7-1 Signal Naming Convention on Both Sides of the Hub Interfaces...................... 103
7-2 Hub Interface 2.0 Length Matching ................................................................... 105
7-3 Hub Interface 2.0 Routing Guidelines for Device Down Solutions .................... 106
7-4 Hub Interface 2.0 Routing Guidelines for Hub Interface Connector
Solutions ........................................................................................................... 106
7-5 Hub Interface 2.0 with Locally Generated Voltage Divider Circuit .................... 107
7-6 Hub Interface 2.0 RCOMP Circuits ................................................................... 108
7-7 8-Bit Hub Interface 1.5 Routing......................................................................... 109
7-8 Hub Interface 1.5 Locally Generated Reference Divider Circuits...................... 110
7-9 Hub Interface 1.5 RCOMP Circuits ................................................................... 111
8-1 Typical PCI/PCI-X Topology ............................................................................. 115
8-2 Typical Hot-Plug Topology ................................................................................ 116
8-3 PCI-X Riser Card Topology............................................................................... 117
8-4 Device Down before PCI-X Riser Card Topology ............................................. 118
8-5 Device Down after PCI-X Riser Card Topology ................................................ 118
8-6 Device Down with Stub before PCI-X Riser Card Topology ............................. 119
8-7 Two Devices Down Card Topology................................................................... 119
8-8 Hot-Plug Clock Topology .................................................................................. 120
8-9 No Hot-Plug Clock Topology............................................................................. 120