64-bit Intel Xeon Processor MP with 1MB L2 Cache Specification Update

42 64-bit Intel
®
Xeon
®
Processor MP with up to 1 MB L2 Cache Specification Update
Specification Clarifications
instruction or the external STPCLK# pin. Note that the assertion of the external DPSLP# pin may
cause the time-stamp counter to stop.
Members of the processor families increment the time-stamp counter differently:
• For Pentium M processors (family [06H], models [09H, 0DH]); for Pentium 4 processors,
Intel Xeon processors (family [0FH], models [00H, 01H, or 02H]); and for P6 family
processors: the time-stamp counter increments with every internal processor clock cycle. The
internal processor clock cycle is determined by the current core-clock to bus-clock ratio. Intel
SpeedStep
®
technology transitions may also impact the processor clock.
• For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and higher]): the
time-stamp counter increments at a constant rate. That rate may be set by the maximum
core-clock to bus-clock ratio of the processor or may be set by the frequency at which the
processor is booted. The specific processor configuration determines the behavior. Constant
TSC behavior ensures that the duration of each clock tick is uniform and supports the use of
the TSC as a wall clock timer even if the processor core changes frequency. This is the
architectural behavior moving forward.
Note: To determine average processor clock frequency, Intel recommends the use of Performance
Monitoring logic to count processor core clocks over the period of time for which the average is
required. See Section 15.10.9 and Appendix A in this manual for more information.
The RDTSC instruction reads the time-stamp counter and is guaranteed to return a monotonically
increasing unique value whenever executed, except for a 64-bit counter wraparound. Intel
guarantees that the time-stamp counter will not wraparound within 10 years after being reset. The
period for counter wrap is longer for Pentium 4, Intel Xeon, P6 family, and Pentium processors.
Normally, the RDTSC instruction can be executed by programs and procedures running at any
privilege level and in virtual-8086 mode. The TSD flag allows use of this instruction to be
restricted to programs and procedures running at privilege level 0. A secure operating system
would set the TSD flag during system initialization to disable user access to the time-stamp
counter. An operating system that disables user access to the time-stamp counter should emulate
the instruction through a user-accessible programming interface.
The RDTSC instruction is not serializing or ordered with other instructions. It does not necessarily
wait until all previous instructions have been executed before reading the counter. Similarly,
subsequent instructions may begin execution before the RDTSC instruction operation is
performed.
The RDMSR and WRMSR instructions read and write the time-stamp counter, treating the
time-stamp counter as an ordinary MSR (address 10H). In the Pentium 4, Intel Xeon, and P6 family
processors, all 64-bits of the time-stamp counter are read using RDMSR (just as with RDTSC).
When WRMSR is used to write the time-stamp counter on processors before family [0FH], models
[03H, 04H]: only the low order 32-bits of the time-stamp counter can be written (the high-order 32
bits are cleared to 0). For family [0FH], models [03H, 04H]: all 64 bits are writeable.
15.10.9 Counting Clocks
The count of cycles, also known as clockticks, forms a the basis for measuring how long a program
takes to execute. Clockticks are also used as part of efficiency ratios like cycles per instruction
(CPI). Processor clocks may stop ticking under circumstances like the following:
• The processor is halted when there is nothing for the CPU to do. For example, the processor
may halt to save power while the computer is servicing an I/O request. When Hyper-Threading
Technology is enabled, both logical processors must be halted for performance-monitoring
counters to be powered down.