64-bit Intel Xeon Processor MP with 1MB L2 Cache Specification Update

36 64-bit Intel
®
Xeon
®
Processor MP with up to 1 MB L2 Cache Specification Update
Errata
When these conditions are met, the processor may incorrectly - and indefinitely - assert a snoop
stall for the Defer Reply transaction. Such an event will block further progress on the FSB.
Implication: If this erratum occurs, the system may hang. Intel has not observed this erratum with any
commercially available system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
J68. The processor may issue Front Side Bus transactions up to 6 clocks after
RESET# is asserted
Problem: The processor may issue transactions beyond the documented 3 Front Side Bus (FSB) clocks and
up to 6 FSB clocks after RESET# is asserted in the case of a warm reset. A warm reset is where the
chipset asserts RESET# when the system is running.
Implication: The processor may issue transactions up to 6 FSB clocks after RESET# is asserted.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
J69. Front Side Bus machine checks may be reported as a result of on-going
transactions during warm reset
Problem: Processor FSB protocol/signal integrity machine checks may be reported if the transactions are
initiated or in-progress during a warm reset. A warm reset is where the chipset asserts RESET#
when the system is running.
Implication: The processor may log FSB protocol/signal integrity machine checks if transactions are allowed to
occur during RESET# assertions.
Workaround: BIOS may clear FSB protocol/signal integrity machine checks for systems/chipsets which do not
block new transactions during RESET# assertions.
Status: For the steppings affected, see the Summary Table of Changes.
J70. Writing the Local Vector Table (LVT) when an interrupt is pending may
cause an unexpected interrupt
Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken on the new
interrupt vector even if the mask bit is set.
Implication: An interrupt may immediately be generated with the new vector when a LVT entry is written, even
if the new LVT entry has the mask bit set. If there is no Interrupt Service Routine (ISR) set up for
that vector the system will GP fault. If the ISR does not do an End of Interrupt (EOI) the bit for
the vector will be left set in the in-service register and mask all interrupts at the same or lower
priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if that vector
was programmed as masked. This ISR routine must do an EOI to clear any unexpected interrupts
that may occur. The ISR associated with the spurious vector does not generate an EOI, therefore
the spurious vector should not be used when writing the LVT.
Status: For the steppings affected, see the Summary Table of Changes.
J71. The processor may issue multiple code fetches to the same cache line for
systems with slow memory
Problem: Systems with long latencies on returning code fetch data from memory, for example BIOS ROM,
may cause the processor to issue multiple fetches to the same cache line, once per each instruction
executed.