64-bit Intel Xeon Processor MP with 1 MB L2 Cache Specification Update

64-bit Intel

Xeon

Processor MP with up to 1 MB L2 Cache Specification Update 27

Errata

The MCA Error Code field of the IA32_MC0_STATUS register gets written by a different

mechanism than the rest of the register. For uncorrectable errors, the other fields in the

IA32_MC0_STATUS register are only updated by the first error. Any further errors that are

detected will update the MCA Error Code field without updating the rest of the register, thereby

leaving the IA32_MC0_STATUS register with stale information.

When a speculative load operation hits the L2 cache and receives a correctable error, the

IA32_MC1_Status Register may be updated with incorrect information. The IA32_MC1_Status

The processor should only log the address for L1 parity errors in the IA32_MC1_Status register if a

valid address is available. If a valid address is not available, the Address Valid bit in the

IA32_MC1_Status register should not be set. In instances where an L1 parity error occurs and the

address is not available because the linear to physical address translation is not complete or an

internal resource conflict has occurred, the Address Valid bit is incorrectly set.

The processor may hang when an instruction code fetch receives a hard failure response from the

system bus. This occurs because the bus control logic does not return data to the core, leaving the

processor empty. IA32_MC0_STATUS MSR does indicate that a hard fail response occurred.

The processor may hang when the following events occur and the machine check exception is

enabled, CR4.MCE=1. A processor that has its STPCLK# pin asserted will internally enter the

Stop Grant State and finally issue a Stop Grant Acknowledge special cycle to the bus. If an

uncorrectable error is generated during the Stop Grant process it is possible for the Stop Grant

special cycle to be issued to the bus before the processor vectors to the machine check handler.

Once the chipset receives its last Stop Grant special cycle it is allowed to ignore any bus activity

from the processors. As a result, processor accesses to the machine check handler may not be

acknowledged, resulting in a processor hang.

Implication: The processor is unable to correctly report and/or recover from certain errors.

Workaround: None identified.

Status: For the steppings affected, see the Summary Table of Changes.

J31. Execution of IRET and INTn instructions may cause unexpected system

behavior

Problem: There is a small window of time, requiring alignment of many internal microarchitectural events,

during which the speculative execution of the IRET or INTn instructions in protected or IA-32e

mode may result in unexpected software or system behavior.

Implication: This erratum may result in unexpected instruction execution, events, interrupts or a system hang

when the IRET instruction is executed. The execution of the INTn instruction may cause debug

breakpoints to be missed.

Workaround: It is possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Table of Changes.

J32. Data breakpoints on the high half of a floating-point line split may not be

captured

Problem: When a floating-point load which splits a 64-byte cache line gets a floating-point stack fault, and a

data breakpoint register maps to the high line of the floating-point load, internal boundary

conditions exist that may prevent the data breakpoint from being captured.

Implication: When this erratum occurs, a data breakpoint will not be captured.

Workaround: None identified.