Intel Xeon Processor MP Specification Update

36 Intel
®
Xeon
®
Processor MP Specification Update
Errata
Implication: The processor will break at the instruction breakpoint address instead of single stepping.
Workaround: Execution after the break will continue if DR7 bit 1 (Global Breakpoint Enable) is manually
cleared.
Status: For the steppings affected, see the Summary Table of Changes.
O59 Changes to CR3 register do not fence pending instruction page
Problem: When software writes to the CR3 register, it is expected that all previous/outstanding code, data
accesses and page walks are completed using the previous value in CR3 register. Due to this
erratum, it is possible that a pending instruction page walk is still in progress, resulting in an access
(to the PDE portion of the page table) that may be directed to an incorrect memory address.
Implication: The results of the access to the PDE will not be consumed by the processor so the return of
incorrect data is benign. However, the system may hang if the access to the PDE does not complete
with data (e.g., infinite number of retries).
Workaround: It is possible for the BIOS to have a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
O60 Simultaneous page-faults at similar page offsets on both logical processors
of an Hyper-Threading Technology enabled processor may cause
application failure
Problem: An incorrect value of CR2 may be presented to one of the logical processors of an HT Technology
enabled processor if a page access fault is encountered on one logical processor in the same clock
cycle that the other logical processor also encounters a page-fault. Both accesses must cross the
same 4 byte aligned offset for this erratum to occur. Only a small percentage of such simultaneous
accesses are vulnerable. The vulnerability of the alignment for any given fault is dependent on the
state of other circuitry in the processor. Additionally, a third fault from an access that occurs
sequentially after one of these simultaneous faults has to be pending at the time of the simultaneous
faults. This erratum is caused by a one-cycle hole in the logic that controls the timing by which a
logical processor is allowed to access an internal asynchronous fault address register. The end
result is that the value of CR2 presented to one logical processor may be corrupted.
Implication: The operating system is likely to terminate the application that generated an incorrect value of
CR2.
Workaround: An operating system or page management software can significantly reduce the already small
possibility of encountering this failure by restarting or retrying the faulting instruction and only
terminate the application on a subsequent failures of the same instruction. It is possible for BIOS to
contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
O61 A 16-bit address wrap resulting from a near branch (jump or call) may cause
an incorrect address to be reported to the #GP exception handler
Problem: If a 16-bit application executes a branch instruction that causes an address wrap to a target address
outside of the code segment, the address of the branch instruction should be provided to the general
protection exception handler. It is possible that, as a result of this erratum, that the general
protection handler may be called with the address of the branch target.
Implication: A 16-bit software environment that is effected by this erratum will see that the address reported by
the exception handler points to the target of the branch rather than the address of the branch
instruction.
Workaround: None at this time.
Status: For the steppings effected, see the Summary Table of Changes.