Intel Xeon Processor LV and ULV Specification Update

Errata
Specification Update 35
AF53. SSE/SSE2 Streaming Store Resulting in a Self-Modifying Code (SMC)
Event May Cause Unexpected Behavior
Problem: An SSE or SSE2 streaming store that results in a Self-Modifying Code (SMC) event
may cause unexpected behavior. The SMC event occurs on a full address match of
code contained in L1 cache.
Implication: Due to this erratum, any of the following events may occur:
1. A data access break point may be incorrectly reported on the instruction pointer
(IP) just before the store instruction.
2. A non-cacheable store can appear twice on the external bus (the first time it will
write only 8 bytes, the second time it will write the entire 16 bytes).
Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AF54. Shutdown Condition May Disable Non-Bootstrap Processors
Problem: When a logical processor encounters an error resulting in shutdown or VMX-Abort,
non-bootstrap processors in the package may be unexpectedly disabled.
Implication: Non-bootstrap logical processors in the package that have not observed the error
condition may be disabled and may not respond to INIT#, SMI#, NMI#, SIPI or other
events.
Workaround: When this erratum occurs, RESET# must be asserted to restore multi-core
functionality.
Status: For the steppings affected, see the Summary Tables of Changes.
AF55. Split Locked Stores May not Trigger the Monitoring Hardware
Problem: Logical processors normally resume program execution following the MWAIT, when
another logical processor performs a write access to a WB cacheable address within
the address range used to perform the MONITOR operation. Due to this erratum, a
logical processor may not resume execution until the next targeted interrupt event or
O/S timer tick following a locked store that spans across cache lines within the
monitored address range.
Implication: The logical processor that executed the MWAIT instruction may not resume execution
until the next targeted interrupt event or O/S timer tick in the case where the
monitored address is written by a locked store which is split across cache lines.
Workaround: Do not use locked stores that span cache lines in the monitored address range.
Status: For the steppings affected, see the Summary Tables of Changes.
AF56. Writing Shared Unaligned Data that Crosses a Cache Line without
Proper Semaphores or Barriers May Expose a Memory Ordering Issue