64-bit Intel Xeon Processorwith 1MB L2 Cache Thermal/Mechanical Design Guidelines

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Processor Thermal Management Logic and Thermal Monitor Features
64-bit Intel
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Xeon™ Processor MP with 1 MB L2 Cache 57
Thermal/Mechanical Design Guidelines
F.1.3 Operation and Configuration
To maintain compatibility with previous generations of processors, which have no integrated
thermal logic, the TCC portion of Thermal Monitor is disabled by default. During the boot process,
the BIOS must enable the TCC; or a software driver may do this after the operating system has
booted. Thermal Monitor or Thermal Monitor 2 feature must be enabled for the processor to
remain within specification.
The TCC feature can be configured and monitored in a number of ways. OEMs are expected to
enable the TCC while using various registers and outputs to monitor the processor thermal status.
The TCC is enabled by the BIOS setting a bit in an MSR (model specific register). Enabling the
TCC allows the processor to maintain a safe operating temperature without the need for special
software drivers or interrupt handling routines. When the TCC has been enabled, processor power
consumption will be reduced within a few hundred clock cycles after the thermal sensor detects a
high temperature, i.e. PROCHOT# assertion. The TCC and PROCHOT# transition to inactive once
the temperature has been reduced below the thermal trip point, although a small time-based
hysteresis has been included to prevent multiple PROCHOT# transitions around the trip point.
External hardware can monitor PROCHOT# and generate an interrupt whenever there is a transition
from active-to-inactive or inactive-to-active. PROCHOT# can also be configured to generate an
internal interrupt which would initiate an OEM supplied interrupt service routine. Regardless of the
configuration selected, PROCHOT# will consistently indicate the thermal status of the processor.
The TCC can also be activated manually using an “on-demand” mode.
F.1.4 Thermal Monitor 2
The 64-bit Intel Xeon processor MP with 1 MB L2 cache also supports an enhanced TCC that works
in conjunction with the existing Thermal Monitor logic. This capability is known as Thermal
Monitor 2. This improved TCC provides a more efficient means for limiting the processor
temperature by reducing the power consumption within the processor.
When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the enhanced
TCC will be activated. The enhanced TCC causes the processor to adjust its operating frequency
(bus-to-core multiplier) and input voltage identification (VID) value. This combination of reduced
frequency and the lowering of VID results in a reduction in processor power consumption.
A processor enabled for Thermal Monitor 2 includes two operating points, each consisting of a
specific operating frequency and voltage. The first operating point represents the normal operating
condition for the processor. The second operating point consists of both a lower operating frequency
and voltage.
When the TCC is activated, the processor automatically transitions to the new frequency. This
transition occurs very rapidly (on the order of 5 microseconds). During the frequency transition, the
processor is unable to service any bus requests, and consequently, all bus traffic is blocked during
the frequency transition. Edge-triggered interrupts will be latched and kept pending until the
processor resumes operation at the new frequency.
Once the new operating frequency is engaged, the processor will transition to the new core operating
voltage by issuing a new VID code to the voltage regulator. The voltage regulator must support
dynamic VID changes in order to support Thermal Monitor 2. During the voltage change, it will be
necessary to transition through multiple VID codes to reach the target operating voltage. Each step
will be one VID table entry (i.e. 12.5 mV steps). The processor continues to execute instructions
during the voltage transition. Operation at the lower voltage reduces both the dynamic and leakage
power consumption of the processor. Once the processor has sufficiently cooled, and the time based