64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus 17
(1 MB and 2 MB L2 Cache Versions) Specification Update
Summary Table of Changes
S81 XXXXXPlan FixRunning in System Management Mode (SMM) and L1 data
cache adaptive mode may cause unexpected system
behavior when SMRAM is mapped to cacheable memory
S82 XXXXXNo FixA 64-bit value of Linear Instruction Pointer (LIP) may be
reported incorrectly in the Branch Trace Store (BTS) memory
record or in the Precise Event Based Sampling (PEBS)
memory record
S83 XXXXXPlan FixIt is possible that two specific invalid opcodes may cause
unexpected memory accesses
S84 XXXXXNo FixAt core-to-bus ratios of 16:1 and above Defer Reply
transactions with non-zero REQb values may cause a Front
Side Bus stall
S85 XXXXXNo FixProcessor may issue Frost Side Bus transactions up to 6
clocks after RESET# is asserted
S86 XXXXXNo FixFront Side Bus machine checks may be reported as a result
of on-going transactions during warm reset
S87 XXXXXNo FixWriting the local vector table (LVT) when an interrupt is
pending may cause an unexpected interrupt
S88 XXXXXNo FixThe processor may issue multiple code fetches to the same
cache line for systems with slow memory
S89 XPlan FixCPUID feature flag reports LAHF/SAHF as unavailable,
however the execution of LAHF/SAHF may not result in an
Invalid Opcode exception
S90 XXXXXNo FixIRET under certain conditions may cause an unexpected
Alignment Check Exception
S91 XFixedUpper 32 bits of ‘From’ address reported through LBR or LER
MSRs, BTMs or BTSs may be incorrect
S1S XXXXXNoFixEXTEST/CLAMP may cause incorrect values to be driven on
processor pins
S92 XXXXXNo FixThe IA32_MC0_STATUS/IA32_MC1_STATUS/
IA32_MC4_STATUS Overflow Bit is not set when multiple
un-correctable machine check errors occur at the same time.
S93 XXXXXNo FixDebug Status Register (DR6) Breakpoint Condition Detected
Flags May be Set Incorrectly.
Errata (Sheet 5 of 5)
No.
D-0/
0F34h
E-0/
0F41h
G-1/
0F49h
N-0/
0F43h
R-0/
0F4Ah
Plans Errata