64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update

64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus 13
(1 MB and 2 MB L2 Cache Versions) Specification Update
Summary Table of Changes
W= Intel
®
Celeron
®
M processor
X=Intel
®
Pentium
®
M processor on 90 nm process with 2 MB L2 cache
Y=Intel
®
Pentium
®
M processor
Z = Mobile Intel
®
Pentium
®
4 processor with 533 MHz system bus
AC = Intel
®
Celeron
®
processor in 478-pin package
The Specification Updates for the Pentium
®
processor, Pentium
®
Pro processor, and other Intel
products do not use this convention.
Errata (Sheet 1 of 5)
No.
D-0/
0F34h
E-0/
0F41h
G-1/
0F49h
N-0/
0F43h
R-0/
0F4Ah
Plans Errata
S1 XXXXXNo FixTransaction is not retired after BINIT#
S2 XXXXXNo FixInvalid opcode 0FFFh requires a ModRM byte
S3 XXXXXNo FixProcessor may hang due to speculative page walks to
non-existent system memory
S4 XXXXXNo FixMemory type of the load lock different from its corresponding
store unlock
S5 XXXXXNo FixMachine Check Architecture error reporting and recovery may
not work as expected
S6 XXXXXNo FixDebug mechanisms may not function as expected
S7 XXXXXNo FixCascading of performance counters does not work correctly
when forced overflow is enabled
S8 XXXXXNo FixEMON event counting of x87 loads may not work as expected
S9 XXXXXNo FixSystem bus interrupt messages without data and which
receive a hard-failure response may hang the processor
S10 XXXXXNo FixThe processor signals page fault exception (#PF) instead of
alignment check exception (#AC) on an unlocked
CMPXCHG8B instruction
S11 XXXXXNo FixFSW may not be completely restored after page fault on
FRSTOR or FLDENV instructions
S12 XXXXXNo FixProcessor issues inconsistent transaction size attributes for
locked operation
S13 XXXXXNo FixWhen the processor is in the system management mode
(SMM), Debug registers may be fully writeable
S14 XXXXXNo FixShutdown and IERR# may result due to a machine check
exception on a Hyper-Threading Technology enabled
processor
S15 XXXXXNo FixProcessor may hang under certain frequencies and 12.5%
STPCLK# duty cycle
S16 XXXXXNo FixSystem may hang if a fatal cache error causes bus write line
(BWL) transaction to occur to the same cache line address as
an outstanding bus read line (BRL) or bus read-invalidate line
(BRIL)
S17 XXXXXNo FixA write to APIC task priority register (TPR) that lowers priority
may seem to have not occurred
S18 XXXXXNo FixParity error in the L1 cache may cause the processor to hang
S19 XX FixedSequence of locked operations can cause two threads to
receive stale data and cause application hang