64-bit Intel Xeon Processor MP with up to 8 MB L3 Cache Specification Update

34 64-bit Intel
®
Xeon
®
Processor MP with up to 8 MB L3 Cache Specification Update
Errata
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
U67 It is possible that two specific invalid opcodes may cause unexpected
memory accesses
Problem: A processor is expected to respond with an undefined opcode (#UD) fault when executing either
opcode 0F 78 or a Grp 6 opcode with bits 5:3 of the Mod/RM field set to 6, however the processor
may respond instead, with a load to an incorrect address.,
Implication: This erratum may cause unpredicatbale system behavior or system hang.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
U68 At core-to-bus ratios of 16:1 and above Defer Reply transactions with non-
zero REQb values may cause a Front Side Bus stall
Problem: Certain processors are likely to hang the Front Side Bus (FSB) if the following conditions are met:
1. A Defer Reply transaction has a REQb[2:0] value of either 010b, 011b, 100b, 110b, or 111b,
and
2. The operating bus ratio is 16:1 or higher.
When these conditions are met, the processor may incorrectly and indefinitely assert a snoop stall
for the Defer Reply transaction. Such an event will block further progress on the FSB.
Implication: If this erratum occurs, the system may hang. Intel has not observed this erratum with any
commercially available system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
U69 The processor may issue Front Side Bus transactions up to 6 clocks after
RESET# is asserted
Problem: The processor may issue transactions beyond the documented 3 Front Side Bus (FSB) clocks and
up to 6 FSB clocks after RESET# is asserted in the case of a warm reset. A warm reset is where the
chipset asserts RESET# when the system is running.
Implication: The processor may issue transactions up to 6 FSB clocks after RESET# is asserted.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
U70 Front Side Bus machine checks may be reported as a result of on-going
transactions during warm reset
Problem: Processor FSB protocol/signal integrity machine checks may be reported if the transactions are
initiated or in-progress during a warm reset. A warm reset is where the chipset asserts RESET#
when the system is running.
Implication: The processor may log FSB protocol/signal integrity machine checks if transactions are allowed to
occur during RESET# assertions.
Workaround: BIOS may clear FSB protocol/signal integrity machine checks for systems/chipsets which do not
block new transactions during RESET# assertions.
Status: For the steppings affected, see the Summary Table of Changes.