VRM 9.1 DC-DC Converter Design Guidelines

Electrical Specifications
8 VRM 9.1 DC-DC Converter Design Guidelines
1.1.3 Output Voltage Tolerance - REQUIRED
The remote sense lines of each VRM should be routed on the system board to a remote sense point
at the geometric center of the processors, where they are connected to each other and to the Vcc
and Vss planes for Intel Xeon processors using the 603 socket. For 64-bit Intel Xeon processor MP
cache remote sense traces, the processor V
CCSENSE
and V
SSSENSE
pins should be connected to test
points on the baseboard in order to probe the die voltage. Unstuffed resistor pads on the baseboard
can be used for this purpose.
The VRM regulates this point as follows:
• VvrmMIN = 0.980 * VID_Setpoint_Voltage - VRM_Output_Current * 0.95 mΩ
• VvrmMAX = VID_Setpoint_Voltage - VRM_Output_Current * 0.95 mΩ
• Vvrm
MIN
and Vvrm
MAX
are VRM voltage regulation requirements measured at the power
plane reference point (VRM remote-sense star connection at the geometric center of the
processor loads on the system board).
• Vvrm
MIN
is the minimum voltage allowed for a given VRM output current.
• Vvrm
MAX
is the maximum voltage allowed for a given VRM output current.
See example load lines in Figure 1-1, Figure 1-2, Figure 1-3, and Figure 1-4 and their
corresponding numerical values in Table 1-2 and Table 1-3. The VRM shall regulate as defined
above for all VID set-points (except during input voltage turn-on and turn-off - see Section 1.1.6
for turn-on and turn-off tolerances).
Voltage tolerance includes:
• Initial DC output voltage set-point error
• Component aging effects
• Output ripple and noise from DC to 100 MHz
• Full ambient temperature range and warm up
• Static operation
• Dynamic output load changes
• Input voltage variations