Intel Xeon Processor Specification Update

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Intel

Xeon

Processor Specification Update 51

Specification Changes

There are no new Specification Changes for this month.

The Specification Changes listed in this section apply to the following documents:

• Intel

Xeon

Processor at 1.40 GHz, 1.50 GHz, 1.70 and 2 GHz Datasheet

(Order Number 249665)

• Intel

Xeon

Processor with 512 KB L2 Cache at 1.80 GHz to 3.0 GHz Datasheet

(Order Number 298642)

• Intel

Xeon

Processor with 533 MHz Front Side Bus at 2 GHz to 3.20 GHz Datasheet (Order

Number 252135)

• Low Voltage Intel

Xeon

Processor at 1.60 GHz to 2.4 GHz Datasheet

(Order Number 273766)

• Intel

64 and IA-32 Intel

Architectures Software Developer’s Manual, Volumes 1, 2A, 2B,

3A, and 3B (Order Numbers 253665, 253666, 253667, and 253668, respectively)

All Specification Changes will be incorporated into a future version of the appropriate Intel

Xeon

processor documentation.

P1 Context ID feature added to processor signature instruction feature

Flags/IA32_MISC_Enable registers

IA32_MISC_ENABLE register, bit 24 status has changed from Reserved to the following

definition:

IA32_MISC_ENABLE – Miscellaneous Enables Register, bit # 24

MSR Address: 01A0h Accessed as a Qword

Default Value: High Dword XXXX XXXXh

Low Dword XXXX XXXX XXXX XXXX XXXX XX00 X0X0 0001b

Access: Read/Write

Type: Shared

IA32_MISC_ENABLE is a 64-bit register accessed only when referenced as a Qword through a

RDMSR or WRMSR instruction.

Bit 24 of the IA32_MISC_ENABLE status has changed from Reserved to the following:

In the Processor Signature Instruction function 1 feature information, bit 10 of ECX register

(ECX[10]) has been assigned as a flag to identify “Context ID feature”. The status has changed

from Reserved to the following:

Bit Descriptions

L1 Data Cache Context Mode (R/W). When set to a ‘1’ this bit places the L1 Data Cache into

shared mode. When set to a ‘0’ (default) this bit places the L1 Data Cache into adaptive mode.

When this bit is set to a ‘0’, adaptive mode, the Page Directory Base Register contained in CR3

must be identical across all logical processors.

Note: If the Context ID feature flag, ECX[10], is not set to a ‘1’ after executing Processor SIgnature

Instruction with EAX = 1, then this feature is not supported and BIOS must not alter the contents of

this bit location.