Intel Xeon Processor LV and ULV Specification Update

Summary Tables of Changes
Specification Update 15
Number
Stepping
Plans
ERRATA
C0
D0
AF67
X
X
No Fix
An Asynchronous MCE During a Far Transfer May Corrupt ESP
AF68
X
X
No Fix
BTM/BTS Branch-From Instruction Address May be Incorrect for
Software Interrupts
AF69
X
X
No Fix
Store to WT Memory Data May be Seen in Wrong Order by Two
Subsequent Loads
AF70
X
X
No Fix
Single Step Interrupts with Floating Point Exception Pending May Be
Mishandled
AF71
X
X
No Fix
Non-Temporal Data Store May be Observed in Wrong Program Order
AF72
X
X
No Fix
Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame
AF73
X
X
No Fix
Unaligned Accesses to Paging Structures May Cause the Processor to Hang
AF74
X
X
No Fix
Microcode Updates Performed During VMX Non-root Operation Could Result in
Unexpected Behavior
AF75
X
X
No Fix
INVLPG Operation for Large (2M/4M) Pages may be Incomplete under Certain
Conditions
AF76
X
X
No Fix
Page Access Bit May be Set Prior to Signaling a Code Segment Limit Fault
AF77
X
X
No Fix
Performance Monitoring Events for Hardware Prefetch Requests (4EH) and
Hardware Prefetch Request Cache Misses (4FH) May Not be Accurate
AF78
X
X
No Fix
EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after Shutdown
AF79
X
X
No Fix
Store Ordering May be Incorrect between WC and WP Memory Types
AF80
X
X
No Fix
A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to Memory-
Ordering Violations
AF81
X
X
No Fix
Corruption of CS Segment Register During RSM While Transitioning From Real
Mode to Protected Mode
Number
SPECIFICATION CHANGES
There are no Specification Changes in this Specification Update revision.
Number
SPECIFICATION CLARIFICATIONS
There are no Specification Clarifications in this Specification Update revision.
Number
DOCUMENTATION CHANGES
There are no Documentation Changes in this Specification Update revision.
§