Intel Xeon Processor LV and ULV Specification Update
Summary Tables of Changes
12 Specification Update
Number
Stepping
Plans
ERRATA
C0
D0
AF1
X
X
No Fix
FST Instruction with Numeric and Null Segment Exceptions May take
Numeric Exception with Incorrect FPU Operand Pointer
AF2
X
X
No Fix
Code Segment Limit Violation May Occur on 4 Gbyte Limit Check
AF3
Errata – Removed.
AF4
X
X
No Fix
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types may use an
Incorrect Data Size or Lead to Memory-Ordering Violations
AF5
X
X
No Fix
Memory Aliasing with Inconsistent A and D Bits May Cause Processor
Deadlock
AF6
X
X
No Fix
VM Bit is Cleared on Second Fault Handled by Task Switch from
Virtual-8086 (VM86)
AF7
X
X
No Fix
Page with PAT (Page Attribute Table) Set to USWC (Uncacheable
Speculative Write Combine) While Associated MTRR (Memory Type
Range Register) Is UC (Uncacheable) May Consolidate to UC
AF8
X
X
No Fix
FPU Operand Pointer May Not be Cleared Following FINIT/FNINIT
AF9
X
X
No Fix
LTR Instruction May Result in Unexpected Behavior
AF10
X
X
No Fix
Invalid Entries in Page-Directory-Pointer-Table Register (PDPTR) May
Cause General Protection (#GP) Exception if the Reserved Bits are Set
to One
AF11
X
X
No Fix
VMCALL When Executed during VMX Root Operation while CPL > 0
May Not Generate #GP Fault
AF12
X
X
No Fix
FP Inexact-Result Exception Flag May Not be Set
AF13
X
X
No Fix
A Locked Data Access that Spans Across Two Pages May Cause the
System to Hang
AF14
X
X
No Fix
MOV With Debug Register Causes Debug Exception
AF15
X
X
No Fix
INIT Does Not Clear Global Entries in the TLB
AF16
X
X
No Fix
Use of Memory Aliasing with Inconsistent Memory Type May Cause
System Hang or a Machine Check Exception
AF17
X
X
No Fix
Machine Check Exception May Occur When Interleaving Code between
Different Memory Types
AF18
X
X
No Fix
Data Prefetch Performance Monitoring Events Can only be Enabled on
a Single Core
AF19
X
X
No Fix
LOCK# Asserted During a Special Cycle Shutdown Transaction May
Unexpectedly De-assert
AF20
X
X
No Fix
Disable Execution-Disable Bit (IA32_MISC_ENABLES [34]) is Shared
Between Cores
AF21
X
X
No Fix
Last Branch Records (LBR) Updates May be Incorrect After a Task
Switch
AF22
X
X
No Fix
Address Reported by Machine-Check Architecture (MCA) on Single-bit
L2 ECC Errors May be Incorrect