Intel Xeon Processor 2.80 GHz Specification Update

Dual-Core Intel
®
Xeon
®
Processor 2.80 GHz Specification Update 27
Errata
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
D48. PDE/PTE Loads and continuous locked updates to the same cache line may
cause a system livelock
Problem: In a multiprocessor configuration, if one processor is continuously doing locked updates to a cache
line that is being accessed by another processor doing a page table walk, the page table walk may
not complete.
Implication: Due to this erratum, the system may livelock until some external event interrupts the locked
update. Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
D49. The processor may issue front side bus transactions up to 6 clocks after
RESET# is asserted
Problem: he processor may issue transactions beyond the documented 3 FSB clocks and up to 6 FSB clocks
after RESET# is asserted in the case of a warm reset. A warm reset is where the chipset asserts
RESET# when the system is running.
Implication: The processor may issue transactions up to 6 FSB clocks after RESET# is asserted.
Status: For the steppings affected, see the Summary Table of Changes.
D50. Front side bus machine checks may be reported as a result of on-going
transactions during warm reset
Problem: Processor FSB protocol/signal integrity machine checks may be reported if the transactions are
initiated or in-progress during a warm reset. A warm reset is where the chipset asserts RESET#
when the system is running.
Implication: The processor may log FSB protocol/signal integrity machine checks if transactions are allowed to
occur during RESET# assertions.
Workaround: BIOS may clear FSB protocol/signal integrity machine checks for systems/chipsets which do not
block new transactions during RESET# assertions.
Status: For the steppings affected, see the Summary Table of Changes.
D51. Entering single logical processor mode via power on configuration may not
work
Problem: When the system uses power on configuration (POC) to enter single logical processor mode on a
dual core processor (by asserting A31# at the deassertion of RESET#), the system may be
susceptible to a variety of failing symptoms including; system hangs and MCERR# or IERR#
assertions.
Implication: POC can not be used to enter single logical processor mode.
Status: For the steppings affected, see the Summary Table of Changes.
D52. Writing the local vector table (LVT) when an interrupt is pending may cause
an unexpected interrupt
Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken on the
new interrupt vector even if the mask bit is set.
Implication: An interrupt may immediately be generated with the new vector when a LVT entry is written, even
if the new LVT entry has the mask bit set. If there is no interrupt service routine (ISR) set up for