Intel Xeon Processor 2.80 GHz Specification Update

Dual-Core Intel
®
Xeon
®
Processor 2.80 GHz Specification Update 23
Errata
D33. FXRSTOR may not restore non-canonical effective addresses on
processors with Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
Enabled
Problem: If an x87 data instruction has been executed with a non-canonical effective address, FXSAVE may
store that non-canonical FP data pointer (FDP) value into the save image. An FXRSTOR
instruction executed with 64-bit operand size may signal a General Protection Fault (#GP) if the
FDP or FP instruction pointer (FIP) is in non-canonical form.
Implication: When this erratum occurs, Intel EM64T enabled systems may encounter an unintended #GP fault.
Workaround: Software should avoid using non-canonical effective addressing in Intel EM64T enabled
processors. BIOS can contain a workaround for this erratum removing the unintended #GP fault on
FXRSTOR.
Status: For the steppings affected, see the Summary Table of Changes.
D34. A push of esp that faults may zero the upper 32 bits of RSP
Problem: In the event that a push ESP instruction, that faults, is executed in compatibility mode, the
processor will incorrectly zero upper 32-bits of RSP.
Implication: A Push of ESP in compatibility mode will zero the upper 32-bits of RSP. Due to this erratum, this
instruction fault may change the contents of RSP. This erratum has not been observed in
commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
D35. Enhanced halt state (C1E) may not be entered in a Hyper-Threading
Technology enabled processor
Problem: If the IA32_MISC_ENABLE MSR (0x1A0) C1E enable bit is not set prior to an INIT event on an
HT Technology enabled system, the processor will not enter C1E until the next SIPI wakeup event
for the second logical processor.
Implication: Due to this erratum, the processor will not enter C1E state.
Workaround: If C1E is supported in the system, the IA32_MISC_ENABLE MSR should be enabled prior to
issuing the first SIPI to the second logical processor.
Status: For the steppings affected, see the Summary Table of Changes.
D36. Checking of page table base address may not match the address bit width
supported by the platform
Problem: If the page table base address, included in the page map level-4 table, page-directory pointer table,
page-directory table or page table, exceeds the physical address range supported by the platform
(e.g. 36-bit) and it is less than the implemented address range (e.g. 40-bit), the processor does not
check if the address is invalid.
Implication: If software sets such invalid physical address in those tables, the processor does not generate a page
fault (#PF) upon access to that virtual address, and the access results in an incorrect read or write. If
BIOS provides only valid physical address ranges to the operating system, this erratum will not
occur.
Workaround: BIOS must provide valid physical address ranges to the operating system.
Status: For the steppings affected, see the Summary Table of Changes.