Intel Xeon Processor 2.80 GHz Specification Update

Dual-Core Intel
®
Xeon
®
Processor 2.80 GHz Specification Update 11
Summary Tables of Changes
D23 x No Fix Memory aliasing of pages as uncacheable memory type and write back (WB) may hang the system
D24 x No Fix
Interactions between the instruction translation lookaside buffer (ITLB) and the instruction streaming
buffer may cause unpredictable software behavior
D25 x No Fix Using STPCLK# and executing code from very slow memory could lead to a system hang
D26 x No Fix Processor provides a 4-byte store unlock after an 8-Byte load lock
D27 x No Fix Data breakpoints on the high half of a floating point line split may not be captured
D28 x No Fix Machine Check exceptions may not update last-exception record MSRs (LERs)
D29 x No Fix MOV CR3 performs incorrect reserved bit checking when in PAE paging
D30 x No Fix
Stores to page tables may not be visible to pagewalks for subsequent loads without serializing or
invalidating the page table entry
D31 x No Fix
Processor may fault when the upper 8 bytes of segment selector is loaded from a far jump through a
call gate via the local descriptor table
D32 x No Fix
Loading a stack segment with a selector that references a non-canonical address can lead to a #SS
fault on a processor supporting Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
D33 x No Fix
FXRSTOR may not restore non-canonical effective addresses on processors with Intel
®
Extended
Memory 64 Technology (Intel
®
EM64T) Enabled
D34 x No Fix A push of esp that faults may zero the upper 32 bits of RSP
D35 x No Fix Enhanced halt state (C1E) may not be entered in a Hyper-Threading Technology enabled processor
D36 x No Fix Checking of page table base address may not match the address bit width supported by the platform
D37 x No Fix
IA32_MCi_STATUS MSR may improperly indicate that additional MCA information may have been
captured
D38 x No Fix
With trap flag (TF) asserted, FP instruction that triggers an unmasked FP exception may take single
step trap before retirement of instruction
D39 x No Fix
Branch trace store (BTS) and precise event based sampling (PEBS) may update memory outside the
BTS/PEBS buffer
D40 x No Fix
Memory ordering failure may occur with snoop filtering third party agents after issuing and completing a
bus write invalidate line (BWIL) or bus locked write (BLW) transaction
D41 x No Fix
Control register 2 (CR2) can be updated during a REP MOVS/STOS instruction with fast strings
enabled
D42 x No Fix REP STOS/MOVS instructions with RCX >= 2^32 may cause a system hang
D43 x No Fix
An REP MOVS or an REP STOS instruction with RCX >= 2^32 may fail to execute to completion or may
write to incorrect memory locations on processors supporting Intel
®
Extended Memory 64 Technology
(Intel
®
EM64T)
D44 x No Fix
An REP LODSB or an REP LODSD or an REP LODSQ instruction with RCX >= 2^32 may cause a
system hang on processors supporting Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
D45 x No Fix Data access which spans both canonical and non-canonical address space may hang system
D46 x No Fix
Running in SMM and L1 data cache adaptive mode may cause unexpected system behavior when
SMRAM is mapped to cacheable memory
D47 x No Fix
A 64-bit value of linear instruction pointer (LIP) may be reported incorrectly in the branch trace store
(BTS) memory record or in the precise event based sampling (PEBS) memory record
D48 x No Fix PDE/PTE Loads and continuous locked updates to the same cache line may cause a system livelock
D49 x No Fix The processor may issue front side bus transactions up to 6 clocks after RESET# is asserted
D50 x No Fix Front side bus machine checks may be reported as a result of on-going transactions during warm reset
D51 x No Fix Entering single logical processor mode via power on configuration may not work
Errata (Sheet 2 of 3)
No. A0 Plans Description