64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
August 2009 Specification Update
Order Number: 302402-024 45
—Intel
®
Xeon™ Processor with 800 MHz System Bus
S79 An REP LODSB or an REP LODSD or an REP LODSQ instruction
with RCX >= 2^32 may cause a system hang on processors
supporting Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
Problem: In IA-32e mode using Intel EM64T-enabled processors, a REP LOSDB or an
REP LODSD or an REP LODSQ instruction executed with the register RCX >=
2^32 may fail to complete execution causing a system hang. Additionally,
there may be no #GP fault due to the non-canonical address in the RSI
register.
Implication: This erratum may cause a system hang on Intel EM64T-enabled platforms.
Intel has not observed this erratum with any commercially available software.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
S80 Data access which spans both canonical and non-canonical
address space may hang system
Problem: If a data access causes a page split across the canonical to non-canonical
address space, the processor may livelock which in turn would cause a system
hang.
Implication: When this erratum occurs, the processor may livelock, resulting in a system
hang. Intel has not observed this erratum with any commercially available
software.
Workaround:None identified.
Status: For the steppings affected, see the Summary Table of Changes.
S81 Running in System Management Mode (SMM) and L1 data cache
adaptive mode may cause unexpected system behavior when
SMRAM is mapped to cacheable memory
Problem: In a HT Technology-enabled system, unexpected system behavior may occur if
a change is made to the value of the CR3 result from an Resume from System
Management (RSM) instruction while in L1 data cache adaptive mode
(IA32_MISC_ENABLES MSR 0x1a0, bit 24). This behavior will only be visible
when SMRAM is mapped into WB/WT cacheable memory on SMM entry and
exit.
Implication: This erratum can have multiple failure symptoms, including incorrect data in
memory. Intel has not observed this erratum with any commercially available
software.
Workaround:Disable L1 data cache adaptive mode by setting the L1 data cache context
mode control bit (bit 24) of the IA32_MISC_ENABLES MSR (0x1a0) to 1.
Status: For the steppings affected, see the Summary Table of Changes.
S82 A 64-bit value of Linear Instruction Pointer (LIP) may be
reported incorrectly in the Branch Trace Store (BTS) memory
record or in the Precise Event Based Sampling (PEBS) memory
record
Problem: On a processor supporting Intel EM64T,