64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

Intel
®
Xeon™ Processor with 800 MHz System Bus—
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
Specification Update August 2009
30 Order Number: 302402-024
S21 Bus locks and SMC detection may cause the processor to
temporarily hang
Problem: The processor may temporarily hang in an HT Technology enabled system, if
one logical processor executes a synchronization loop that includes one or
more bus locks and is waiting for release by the other logical processor. If the
releasing logical processor is executing instructions that are within the
detection range of the self-modifying code (SMC) logic, then the processor
may be locked in the synchronization loop until the arrival of an interrupt or
other event.
Implication: If this erratum occurs in an HT Technology enabled system, the application
may temporarily stop making forward progress. Intel has not observed this
erratum with any commercially available software.
Workaround:None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
S22 Incorrect physical address size returned by CPUID instruction
Problem: The CPUID instruction Function 80000008H (Extended Address Sizes Function)
returns the address sizes supported by the processor in the EAX register. This
Function returns an incorrect physical address size value of 40 bits. The
correct physical address size is 36 bits.
Implication: Function 80000008H returns an incorrect physical address size value of 40
bits.
Workaround:None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
S23 Incorrect debug exception (#DB) may occur when a data
breakpoint is set on an FP instruction
Problem: The default microcode floating-point event handler routine executes a series of
loads to obtain data about the FP instruction that is causing the FP event. If a
data breakpoint is set on the instruction causing the FP event, the load in the
microcode routine will trigger the data breakpoint resulting in a debug
exception.
Implication: An incorrect debug exception (#DB) may occur if data breakpoint is placed on
an FP instruction. Intel has not observed this erratum with any commercially
available software or system.
Workaround:None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
S24 xAPIC may not report some illegal vector errors
Problem: The local xAPIC has an error status register, which records all errors it detects.
Bit 6 of this register, the receive Illegal Vector bit, is set when the local xAPIC
detects an illegal vector in a message that it receives. When an illegal vector
error is received on the same internal clock that the error status register is
being written due to a previous error, bit 6 does not get set and illegal vector
errors are not flagged.
Implication: The xAPIC may not report some Illegal Vector errors when they occur at
approximately the same time as other xAPIC errors. The other xAPIC errors
will continue to be reported.