Intel Xeon Processor MP Specification Update

Intel
®
Xeon
®
Processor MP Specification Update 39
Errata
O70 Missing Stop Grant Acknowledge special bus cycle may cause a system
hang
Problem: If a Stop Grant Acknowledge special bus cycle is deferred by the processor for a period of time
long enough for the chipset to de-assert and then re-assert STPCLK# signal, a processor supporting
Hyper-Threading Technology may fail to detect the de-assertion and re-assertion of STPCLK#
signal. When this occurs, the processor will not issue a Stop Grant Acknowledge special bus cycle
in response to the second STPCLK# assertion.
Implication: When this erratum occurs in an Hyper-Threading Technology enabled system, it may cause a
system hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
O71 Machine check exceptions may not update Last-Exception Record MSRs
(LERs)
Problem: The Last-Exception Record MSRs (LERs) may not get updated when machine check exceptions
(MCE) occur.
Implication: When this erratum occurs, the LER may not contain information relating to the MCE. They will
contain information relating to the exception prior to the MCE.
Workaround: None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
O72 Stores to page tables may not be visible to page walks for subsequent loads
without serializing or invalidating the page table entry
Problem: Under rare timing circumstances, a page table load on behalf of a programmatically younger
memory access may not get data from a programmatically older store to the page table entry if
there is not a fencing operation or page translation invalidate operation between the store and the
younger memory access. Refer to the IA-32 Intel
®
Architecture Software Developer’s Manual for
the correct way to update page tables. Software that conforms to the IA-32 Intel
®
Architecture
Software Developer’s Manual will operate correctly.
Implication: If the guidelines in the IA-32 Intel
®
Architecture Software Developer’s Manual are not followed,
stale data may be loaded into the processor's translation lookaside buffer (TLB) and used for
memory operations. This erratum has not been observed with any commercially available software.
Workaround: The guidelines in the IA-32 Intel
®
Architecture Software Developer’s Manual should be followed.
Status: For the steppings affected, see the Summary Table of Changes.
O73 A timing marginality in the Arithmetic Logic Unit (ALU) may cause
indeterminate behavior
Problem: A timing marginality may exist in the clocking of the ALU which leads to a slowdown in the speed
of the circuit’s operation. This could lead to incorrect behavior of the ALU.
Implication: When this erratum occurs, unpredictable application behavior and/or system hang may occur.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.