Intel Xeon Processor MP Specification Update

24 Intel
®
Xeon
®
Processor MP Specification Update
Errata
• When a data breakpoint is set on the ninth and/or tenth byte(s) of a floating point store using
the Extended Real data type, and an unmasked floating point exception occurs on the store, the
break point will not be captured.
• When any instruction has multiple debug register matches, and any one of those debug
registers is enabled in DR7, all of the matches should be reported in DR6 when the processor
goes to the debug handler. This is not true during a REP instruction. As an example, during
execution of a REP MOVSW instruction the first iteration a load matches DR0 and DR2 and
sets DR6 as FFFF0FF5h. On a subsequent iteration of the instruction, a load matches only
DR0. The DR6 register is expected to still contain FFFF0FF5h, but the processor will update
DR6 to FFFF0FF1h.
A Data breakpoint that is set on a load to UC memory may be ignored due to an internal segment
register access conflict. In this case the system will continue to execute instructions, bypassing the
intended breakpoint. Avoiding having instructions that access segment descriptor registers, e.g.,
LGDT, LIDT close to the UC load, and avoiding serialized instructions before the UC load will
reduce the occurrence of this erratum.
Implication: Certain debug mechanisms do not function as expected on the processor.
Workaround: None at this time.
Status: For the steppings effected, see the Summary Table of Changes.
O13 Processor may timeout waiting for a device to respond after 0.67 seconds
Problem: The PCI 2.1 target initial latency specification allows two seconds for a device to respond during
initialization-time. The processor may timeout after only approximately 0.67 seconds. When the
processor times out it will hang with IERR# asserted. PCI devices that take longer than 0.67
seconds to initialize may not be initialized properly.
Implication: System may hang with IERR# asserted.
Workaround: Due to the long initialization time observed on some commercially available PCI cards, it may be
necessary to disable the timeout counter during the PCI initialization sequence. This can be
accomplished by temporarily setting Bit 5 of the MISC_ENABLES_MSR located at address 1A0H
to 1 for all processor in the system. This model specific register (MSR) is software visible but
should only be set for the duration of the PCI initialization sequence. It is necessary to re-enable the
timeout counter by clearing this bit after completing the PCI initialization sequence. CAUTION:
The processor's Thermal Monitor feature may not function if the timeout counter is not re-enabled
after completing the PCI initialization.
After the system is fully initialized, this erratum may occur either when a PCI device is hot added
into the system or when a PCI device is transitioned from D3 cold. System software responsible for
completing the hot add and the power state transition from D3 cold should allow for a delay of the
target initial latency prior to initiating configuration accesses to the PCI device.
Status: For the steppings effected, see the Summary Table of Changes.
O14 Cascading of performance counters does not work correctly when forced
overflow is enabled
Problem: The performance counters are organized into pairs. When the CASCADE bit of the CCCR is set, a
counter that overflows will continue to count in the other counter of the pair. The FORCE_OVF bit
forces the counters to overflow on every non-zero increment. When the FORCE_OVF bit is set, the
counter overflow bit will be set but the counter no longer cascades.
Implication: The performance counters do not cascade when the FORCE_OVF bit is set.
Workaround: None at this time.
Status: For the steppings effected, see the Summary Table of Changes.