64-bit Intel Xeon Processor MP with 1 MB L2 Cache Specification Update

28 64-bit Intel
®
Xeon
®
Processor MP with up to 1 MB L2 Cache Specification Update
Errata
Status: For the steppings affected, see the Summary Table of Changes.
J33. Machine check exceptions may not update Last-exception Record MSRs
(LERs)
Problem: The Last-Exception Record MSRs (LERs) may not get updated when Machine Check Exceptions
occur.
Implication: When this erratum occurs, the LER may not contain information relating to the machine check
exception. They will contain information relating to the exception prior to the machine check
exception.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
J34. MOV CR3 performs incorrect reserved bit checking when in PAE paging
Problem: The MOV CR3 instruction should perform reserved bit checking on the upper unimplemented
address bits. This checking range should match the address width reported by CPUID instruction
0x8000008. This erratum applies whenever PAE is enabled.
Implication: Software that sets the upper address bits on a MOV CR3 instruction and expects a fault may fail.
This erratum has not been observed with commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
J35. Stores to page tables may not be visible to pagewalks for subsequent loads
without serializing or invalidating the page table entry
Problem: Under rare timing circumstances, a page table load on behalf of a programmatically younger
memory access may not get data from a programmatically older store to the page table entry if
there is not a fencing operation or page translation invalidate operation between the store and the
younger memory access. Refer to the IA-32 Intel
®
Architecture Software Developer’s Manual for
the correct way to update page tables. Software that conforms to the Software Developer's Manual
will operate correctly.
Implication: If the guidelines in the IA-32 Intel
®
Architecture Software Developer’s Manual are not followed,
stale data may be loaded into the processor's Translation Lookaside Buffer (TLB) and used for
memory operations. This erratum has not been observed with any commercially available software.
Workaround: The guidelines in the IA-32 Intel
®
Architecture Software Developer’s Manual should be followed.
Status: For the steppings affected, see the Summary Table of Changes.
J36. Recursive page walks may cause a system hang
Problem: A page walk, accessing the same page table entry multiple times but at different levels of the page
table, which causes the page table entry to have its Access bit set may result in a system hang.
Implication: When this erratum occurs, the system may experience a hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
J37. VERR/VERW instructions may cause #GP fault when descriptor is in
non-canonical space
Problem: If a descriptor referenced by the selector specified for the VERR or VERW instructions is in
non-canonical space, it may incorrectly cause a #GP fault on a processor supporting Intel EM64T.