Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-59

INSTRUCTION FORMATS AND ENCODINGS

B.6 P6 FAMILY INSTRUCTION FORMATS AND

ENCODINGS

Table B-20 shows the formats and encodings for several instructions that were intro-

duced into the IA-32 architecture in the P6 family processors.

Table B-20. Formats and Encodings of P6 Family Instructions

Instruction and Format Encoding

CMOVcc – Conditional Move

register2 to register1 0000 1111: 0100 tttn : 11 reg1 reg2

memory to register 0000 1111 : 0100 tttn : mod reg r/m

FCMOVcc – Conditional Move on EFLAG

move if below (B) 11011 010 : 11 000 ST(i)

move if equal (E) 11011 010 : 11 001 ST(i)

move if below or equal (BE) 11011 010 : 11 010 ST(i)

move if unordered (U) 11011 010 : 11 011 ST(i)

move if not below (NB) 11011 011 : 11 000 ST(i)

move if not equal (NE) 11011 011 : 11 001 ST(i)

move if not below or equal (NBE) 11011 011 : 11 010 ST(i)

move if not unordered (NU) 11011 011 : 11 011 ST(i)

FCOMI – Compare Real and Set EFLAGS 11011 011 : 11 110 ST(i)

FXRSTOR – Restore x87 FPU, MMX, SSE,

and SSE2 State

0000 1111:1010 1110: mod

001 r/m

FXSAVE – Save x87 FPU, MMX, SSE, and

SSE2 State

0000 1111:1010 1110: mod

000 r/m

SYSENTER – Fast System Call 0000 1111:0011 0100

SYSEXIT – Fast Return from Fast System

Call

0000 1111:0011 0101

NOTES:

1. For FXSAVE and FXRSTOR, “mod = 11” is reserved.