Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-50 Vol. 2B
INSTRUCTION FORMATS AND ENCODINGS
immediate8 and byteregister 0100 000B 1111 0110 : 11 000 bytereg :
imm8
immediate32 and qwordregister 0100 100B 1111 0111 : 11 000 bytereg :
imm8
immediate and AL, AX, or EAX 0100 000B 1010 100w : imm
immediate32 and RAX 0100 1000 1010 1001 : imm32
immediate and memory 0100 00XB 1111 011w : mod 000 r/m : imm
immediate8 and memory8 0100 1000 1111 0110 : mod 000 r/m : imm8
immediate32 and memory64 0100 1000 1111 0111 : mod 000 r/m : imm32
UD2 – Undefined instruction 0000 FFFF : 0000 1011
VERR – Verify a Segment for Reading
register 0100 000B 0000 1111 : 0000 0000 : 11 100
reg
memory 0100 00XB 0000 1111 : 0000 0000 : mod
100 r/m
VERW – Verify a Segment for Writing
register 0100 000B 0000 1111 : 0000 0000 : 11 101
reg
memory 0100 00XB 0000 1111 : 0000 0000 : mod
101 r/m
WAIT – Wait 1001 1011
WBINVD – Writeback and Invalidate Data
Cache
0000 1111 : 0000 1001
WRMSR – Write to Model-Specific Register
write EDX:EAX to ECX specified MSR 0000 1111 : 0011 0000
write RDX[31:0]:RAX[31:0] to RCX specified
MSR
0100 1000 0000 1111 : 0011 0000
XADD – Exchange and Add
register1, register2 0100 0R0B 0000 1111 : 1100 000w : 11 reg2
reg1
byteregister1, byteregister2 0100 0R0B 0000 1111 : 1100 0000 : 11
bytereg2 bytereg1
qwordregister1, qwordregister2 0100 0R0B 0000 1111 : 1100 0001 : 11
qwordreg2 qwordreg1
Table B-15. General Purpose Instruction Formats and Encodings
for 64-Bit Mode (Contd.)
Instruction and Format Encoding