Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-220 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
PUSHF/PUSHFD—Push EFLAGS Register onto the Stack
Description
Decrements the stack pointer by 4 (if the current operand-size attribute is 32) and
pushes the entire contents of the EFLAGS register onto the stack, or decrements the
stack pointer by 2 (if the operand-size attribute is 16) and pushes the lower 16 bits
of the EFLAGS register (that is, the FLAGS register) onto the stack. These instruc-
tions reverse the operation of the POPF/POPFD instructions.
When copying the entire EFLAGS register to the stack, the VM and RF flags (bits 16
and 17) are not copied; instead, the values for these flags are cleared in the EFLAGS
image stored on the stack. See Chapter 3 of the Intel
®
64 and IA-32 Architectures
Software Developer’s Manual, Volume 1, for more information about the EFLAGS
register.
The PUSHF (push flags) and PUSHFD (push flags double) mnemonics reference the
same opcode. The PUSHF instruction is intended for use when the operand-size
attribute is 16 and the PUSHFD instruction for when the operand-size attribute is 32.
Some assemblers may force the operand size to 16 when PUSHF is used and to 32
when PUSHFD is used. Others may treat these mnemonics as synonyms
(PUSHF/PUSHFD) and use the current setting of the operand-size attribute to deter-
mine the size of values to be pushed from the stack, regardless of the mnemonic
used.
In 64-bit mode, the instruction’s default operation is to decrement the stack pointer
(RSP) by 8 and pushs RFLAGS on the stack. 16-bit operation is supported using the
operand size override prefix 66H. 32-bit operand size cannot be encoded in this
mode. When copying RFLAGS to the stack, the VM and RF flags (bits 16 and 17) are
not copied; instead, values for these flags are cleared in the RFLAGS image stored on
the stack.
When in virtual-8086 mode and the I/O privilege level (IOPL) is less than 3, the
PUSHF/PUSHFD instruction causes a general protection exception (#GP).
In the real-address mode, if the ESP or SP register is 1 when PUSHF/PUSHFD instruc-
tion executes: an #SS exception is generated but not delivered (the stack error
reported prevents #SS delivery). Next, the processor generates a #DF exception and
enters a shutdown state as described in the #DF discussion in Chapter 5 of the Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
9C PUSHF Valid Valid Push lower 16 bits of EFLAGS.
9C PUSHFD N.E. Valid Push EFLAGS.
9C PUSHFQ Valid N.E. Push RFLAGS.