Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B 4-117
INSTRUCTION SET REFERENCE, N-Z
PMULHW—Multiply Packed Signed Integers and Store High Result
Description
Performs a SIMD signed multiply of the packed signed word integers in the destina-
tion operand (first operand) and the source operand (second operand), and stores
the high 16 bits of each intermediate 32-bit result in the destination operand.
(Figure 4-3 shows this operation when using 64-bit operands.) The source operand
can be an MMX technology register or a 64-bit memory location, or it can be an XMM
register or a 128-bit memory location. The destination operand can be an MMX tech-
nology register or an XMM register.
n 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Operation
PMULHW instruction with 64-bit operands:
TEMP0[31:0] ← DEST[15:0]
∗ SRC[15:0]; (* Signed multiplication *)
TEMP1[31:0] ← DEST[31:16]
∗ SRC[31:16];
TEMP2[31:0] ← DEST[47:32]
∗ SRC[47:32];
TEMP3[31:0] ← DEST[63:48]
∗ SRC[63:48];
DEST[15:0] ← TEMP0[31:16];
DEST[31:16] ← TEMP1[31:16];
DEST[47:32] ← TEMP2[31:16];
DEST[63:48] ← TEMP3[31:16];
PMULHW instruction with 128-bit operands:
TEMP0[31:0] ← DEST[15:0]
∗ SRC[15:0]; (* Signed multiplication *)
TEMP1[31:0] ← DEST[31:16]
∗ SRC[31:16];
TEMP2[31:0] ← DEST[47:32]
∗ SRC[47:32];
TEMP3[31:0] ← DEST[63:48]
∗ SRC[63:48];
TEMP4[31:0] ← DEST[79:64]
∗ SRC[79:64];
TEMP5[31:0] ← DEST[95:80]
∗ SRC[95:80];
TEMP6[31:0] ← DEST[111:96]
∗ SRC[111:96];
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
0F E5 /r PMULHW mm,
mm/m64
Valid Valid Multiply the packed signed word
integers in mm1 register and
mm2/m64, and store the high 16
bits of the results in mm1.
66 0F E5 /r PMULHW xmm1,
xmm2/m128
Valid Valid Multiply the packed signed word
integers in xmm1 and
xmm2/m128, and store the high
16 bits of the results in xmm1.