Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B 4-99
INSTRUCTION SET REFERENCE, N-Z
DEST[127:120] ← DEST[127:120];
ELSE
DEST[127:120] ← SRC[127:120]; FI;
Intel C/C++ Compiler Intrinsic Equivalent
PMAXUB __m64 _mm_max_pu8(__m64 a, __m64 b)
PMAXUB __m128i _mm_max_epu8 ( __m128i a, __m128i b)
Flags Affected
None.
Numeric Exceptions
None.
Protected Mode Exceptions
#GP(0) If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.
(128-bit operations only) If a memory operand is not aligned on
a 16-byte boundary, regardless of segment.
#SS(0) If a memory operand effective address is outside the SS
segment limit.
#UD If CR0.EM[bit 2] = 1.
(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.
(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.
#NM If CR0.TS[bit 3] = 1.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#PF(fault-code) If a page fault occurs.
#AC(0) (64-bit operations only) If alignment checking is enabled and an
unaligned memory reference is made while the current privilege
level is 3.
Real-Address Mode Exceptions
#GP(0) (128-bit operations only) If a memory operand is not aligned on
a 16-byte boundary, regardless of segment.
If any part of the operand lies outside of the effective address
space from 0 to FFFFH.
#UD If CR0.EM[bit 2] = 1.
(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.
(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.