Mobile Intel Pentium 4 Processor with 533 MHz System Bus Specification Update

R
Specification Update 9
Stepping
NO.
D1
Plans ERRATA
Z18 X NoFix
IA32_MC0_ADDR and IA32_MC0_MISC registers will contain invalid or stale data
following a Data, Address, or Response Parity Error
Z19 X NoFix Processor may hang under certain frequencies and 12.5% STPCLK# duty cycle
Z20 X NoFix
System may hang if a fatal cache error causes Bus Write Line (BWL) transaction to
occur to the same cache line address as an outstanding Bus Read Line (BRL) or
Bus Read-Invalidate Line (BRIL)
Z21 X NoFix Simultaneous assertion of A20M# and INIT# may result in incorrect data fetch
Z22 X NoFix A Write to APIC Registers Sometimes May Appear to Have Not Occurred
Z23 X PlanFix STPCLK# Signal Assertion under Certain Conditions May Cause a System Hang
Z24 X NoFix Parity Error in the L1 Cache may Cause the Processor to Hang
Z25 X NoFix
Disabling a Local APIC Disables Both Logical Processor APICs on a Hyper-
Threading Technology Enabled Processor
Z26 X NoFix
STPCLK Throttling and Executing Code from Very Slow Memory Could Lead to a
System Hang
Z27 X NoFix
The State of the Resume Flag (RF Flag) in a Task-State Segment (TSS) May be
Incorrect
Z28 X NoFix Changes to CR3 Register do not Fence Pending Instruction Page Walks
Z29 X PlanFix
Simultaneous Page Faults at Similar Page Offsets on Both Logical Processors of a
Hyper-Threading Technology Enabled Processor May Cause Application Failure
Z30 X NoFix
System Bus Interrupt Messages without Data that Receive a HardFailure
Response May Hang the Processor
Z31 X NoFix Memory Type of the Load Lock Different from its Corresponding Store Unlock
Z32 X NoFix
Shutdown and IERR# May Result Due to a Machine Check Exception on a Hyper-
Threading Technology Enabled Processor
Z33 X NoFix
A 16-bit Address Wrap Resulting from a Near Branch (Jump or Call) May Cause an
Incorrect Address to Be Reported to the #GP Exception Handler
Z34 X NoFix Locks and SMC Detection May Cause the Processor to Temporarily Hang
Z35 X NoFix
Incorrect Debug Exception (#DB) May Occur When a Data Breakpoint is set on an
FP Instruction
Z36 X NoFix xAPIC May Not Report Some Illegal Vector Errors
Z37 X PlanFix
Incorrect Duty Cycle is Chosen when On-Demand Clock Modulation is Enabled in a
Processor Supporting Hyper-Threading Technology
Z38 X NoFix
Memory Aliasing of Pages as Uncacheable Memory Type and Write Back (WB)
May Hang the System
Z39 X PlanFix
A Timing Marginality in the Instruction Decoder Unit May Cause an Unpredictable
Application Behavior and/or System Hang
Z40 X NoFix Missing Stop Grant Acknowledge Special Bus Cycle May Cause a System Hang
Z41 X PlanFix
A Timing Maginality in the Arithmetic Logic Unit (ALU) May Cause Indeterminate
Behavior
Z42 X NoFix
With TF (Trap Flag) Asserted, FP Instruction That Triggers an Unmasked FP
Exception May Take Single Step Trap Before Retirement of Instruction