Mobile Intel Pentium 4 Processor with 533 MHz System Bus Specification Update

Specification Update 23

Z25.

Disabling a Local APIC Disables Both Logical Processor APICs on a Hyper-

Threading Technology Enabled Processor

Problem: Disabling a local APIC on one logical processor of a Hyper-Threading Technology enabled processor

by clearing bit 11 of the IA32_APIC_BASE MSR will effectively disable the local APIC on the other

logical processor.

Implication: Disabling a local APIC on one logical processor prevents the other logical processor from sending or

receiving interrupts. Multiprocessor Specification compliant BIOSs and multiprocessor operating

systems typically leave all local APICs enabled preventing any end-user visible impact from this

erratum.

Workaround: Do not disable the local APICs in a Hyper-Threading Technology enabled processor.

Status: For the steppings affected, see the Summary Tables of Changes.

Z26.

STPCLK Throttling and Executing Code From Very Slow Memory Could Lead to

a System Hang

Problem: The system may hang when the following conditions are met:

1. Periodic STPCLK mechanism is enabled via the chipset

2. Hyper-Threading Technology is enabled

3. One logical processor is waiting for an event (i.e. hardware interrupt)

4. The other logical processor executes code from very slow memory such that every code fetch is

deferred long enough for the STPCLK to be re-asserted

Implication: If this erratum occurs, the processor will go into and out of the sleep state without making forward

progress, as the logical processor will not be able to service any pending event. This erratum has not

been observed in any commercial platform running commercial software.

Workaround: None

Status: For the steppings affected, see the Summary Tables of Changes.

Z27.

The State of the Resume Flag (RF Flag) in a Task-State Segment (TSS) May be

Incorrect

Problem: After executing a JMP instruction to the next (or other) task through a hardware task switch, it is

possible for the state of the RF flag (in the EFLAGS register image) to be incorrect.

Implication: The RF flag is normally used for code breakpoint management during debug of an application. It is not

typically used during normal program execution. Code breakpoints or single step debug behavior in the

presence of hardware task switches, therefore, may be unpredictable as a result of this erratum. This

erratum has not been observed in commercially available software.

Workaround: None.

Status: For the steppings affected, see the Summary Tables of Changes.