Mobile Intel Pentium 4 Processor with 533 MHz System Bus Specification Update

R
22 Specification Update
Z22.
A Write to APIC Registers Sometimes May Appear to Have Not Occurred
Problem: In respect to the retirement of instructions, stores to the uncacheable memory-based APIC register space
are handled in a non-synchronized way. For example if an instruction that masks the interrupt flag, e.g.
CLI, is executed soon after an uncacheable write to the Task Priority Register (TPR) that lowers the
APIC priority, the interrupt masking operation may take effect before the actual priority has been
lowered. This may cause interrupts whose priority is lower than the initial TPR, but higher than the final
TPR, to not be serviced until the interrupt flag is finally cleared, i.e. by STI instruction. Interrupts will
remain pending and are not lost.
Implication: In this example the processor may allow interrupts to be accepted but may delay their service.
Workaround: This non-synchronization can be avoided by issuing an APIC register read after the APIC register write.
This will force the store to the APIC register before any subsequent instructions are executed. No
commercial operating system is known to be impacted by this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
Z23.
STPCLK# Signal Assertion under Certain Conditions May Cause a System Hang
Problem: The assertion of STPCLK# signal before a logical processor awakens from the "Wait-for-SIPI" state for
the first time, may cause a system hang. A processor supporting Hyper-Threading Technology may fail
to initialize appropriately, and may not issue a Stop Grant Acknowledge special bus cycle in response
to the second STPCLK# assertion.
Implication: When this erratum occurs in a Hyper-Threading Technology enabled system, it may cause a
system hang.
Workaround: BIOS should initialize the second thread of the processor supporting Hyper-Threading Technology prior
to STPCLK# assertion. Additionally, it is possible for the BIOS to contain a workaround for this
erratum.
Status: For the steppings affected, see the Summary of Tables of Changes.
Z24.
Parity Error in the L1 Cache May Cause the Processor to Hang
Problem: If a locked operation accesses a line in the L1 cache that has a parity error, it is possible that the
processor may hang while trying to evict the line.
Implication: If this erratum occurs, it may result in a system hang. Intel has not observed this erratum with any
commercially available software.
Workaround: None.
Status: For the steppings affected, see the Summary Tables of Changes.