R Mobile Intel® Pentium® 4 Processor with 533 MHz System Bus Specification Update January 2006 Notice: The Mobile Intel® Pentium® 4 processor with 533 MHz system bus may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
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R Contents Revision History................................................................................................................... 4 Preface ................................................................................................................................ 5 Summary Tables of Changes.............................................................................................. 7 Identification Information ..............................................................................
R Revision History Version Description Date of Revision -001 Initial Release June 2003 -002 Added Erratum Z29. July 2003 -003 Updated Errata Z25. Added Errata Z30. August 2003 -004 Added Errata Z31, Z32, Z33, and Z34. September 2003 -005 Updated Mobile Intel Pentium 4 processor Idetification Information table (added 3.20 GHz and S-spec for HT parts) September 2003 -006 Added Errarta Z35. October 2003 -007 Updated Errata Z35. Added Errata Z36.
R Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata, specification clarifications, and specification changes and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
R Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics, e.g., core speed, L2 cache size, package type, etc. as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number Errata are design defects or errors. Errata may cause the mobile Intel® Pentium® processor’s behavior to deviate from published specifications.
R Summary Tables of Changes The following table indicates the Errata, Documentation Changes, Specification Clarifications, or Specification Changes that apply to Intel Pentium 4 processors. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or specification changes as noted.
R M = Mobile Intel® Celeron® processor N = Intel® Pentium® 4 processor O = Intel® Xeon® processor MP P = Intel® Xeon® processor Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading Technology on 90-nm technology process R = Intel® Pentium® 4 processor on 90 nm process S = Intel® Xeon® Processor with 800 MHz System Bus T = Mobile Intel® Pentium® 4 processor – M V = Intel® Celeron® processor in the 478-Pin Package W = Intel® Celeron® M processor X = Intel® Pentium® M processor on 90 nm process w
R Stepping NO. D1 Plans Z18 X NoFix IA32_MC0_ADDR and IA32_MC0_MISC registers will contain invalid or stale data following a Data, Address, or Response Parity Error Z19 X NoFix Processor may hang under certain frequencies and 12.
R Stepping NO.
R Identification Information The Mobile Intel® Pentium® 4 processor can be identified by the following values: Family1 Model2 Brand ID3 1111 0010 00001110 1111 0010 00001111 NOTE: 1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan. 2.
R Component Marking Information Figure 1.
R Errata Z1. I/O Restart in SMM May Fail after Simultaneous Machine Check Exception (MCE) Problem: If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed, and if the data for this instruction becomes corrupted, the processor will signal a Machine Check Exception (MCE). If the instruction is directed at a device that is powered down, the processor may also receive an assertion of SMI#.
R Z3. Transaction Is Not Retried after BINIT# Problem: If the first transaction of a locked sequence receives a HITM# and DEFER# during the snoop phase it should be retried and the locked sequence restarted. However, if BINIT# is also asserted during this transaction, it will not be retried. Implication: When this erratum occurs, locked transactions will unexpectedly not be retried. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. Z4.
R Z6. The Processor Flags #PF Instead of #AC on an Unlocked CMPXCHG8B Instruction Problem: If a data page fault (#PF) and alignment check fault (#AC) both occur for an unlocked CMPXCHG8B instruction, then #PF will be flagged. Implication: Software that depends #AC before #PF will be affected since #PF is flagged in this case. Workaround: Remove the software’s dependency on the fact that #AC has precedence over #PF.
R Z9. MCA Error Code Field in IA32_MC0_STATUS Register May become out of Sync with the Rest of the Register Problem: The MCA Error Code field of the IA32_MC0_STATUS register gets written by a different mechanism than the rest of the register. For uncorrectable errors, the other fields in the IA32_MC0_STATUS register are only updated by the first error. Any subsequent errors cause the Overflow Error bit to be asserted until this register is cleared.
R registers, e.g., LGDT, LIDT close to the UC load, and avoiding serialized instructions before the UC load will reduce the occurrence of this erratum. Implication: Certain debug mechanisms do not function as expected on the processor. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. Z12.
R - If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed, and if the data for this instruction becomes corrupted, the processor will signal a Machine Check Exception (MCE). If the instruction is directed at a device that is powered down, the processor may also receive an assertion of SMI#. Since MCEs have higher priority, the processor will call the MCE handler, and the SMI# assertion will remain pending.
R Z13. Cascading of Performance Counters Does Not Work Correctly When Forced Overflow Is Enabled Problem: The performance counters are organized into pairs. When the CASCADE bit of the Counter Configuration Control Register (CCCR) is set, a counter that overflows will continue to count in the other counter of the pair. The FORCE_OVF bit forces the counters to overflow on every non-zero increment. When the FORCE_OVF bit is set, the counter overflow bit will be set but the counter no longer cascades.
R Z16. Processor Issues Inconsistent Transaction Size Attributes for Locked Operation Problem: When the processor is in the Page Address Extension (PAE) mode and detects the need to set the Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte load lock onto the system bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte store unlock occurs.
R Z19. Processor May Hang under Certain Frequencies and 12.5% STPCLK# Duty Cycle Problem: If a system de-asserts STPCLK# at a 12.5% duty cycle, the processor is running below 2 GHz, and the processor thermal control circuit (TCC) on-demand clock modulation is active, the processor may hang. This erratum does not occur under the automatic mode of the TCC. Implication: When this erratum occurs, the processor will hang.
R Z22. A Write to APIC Registers Sometimes May Appear to Have Not Occurred Problem: In respect to the retirement of instructions, stores to the uncacheable memory-based APIC register space are handled in a non-synchronized way. For example if an instruction that masks the interrupt flag, e.g. CLI, is executed soon after an uncacheable write to the Task Priority Register (TPR) that lowers the APIC priority, the interrupt masking operation may take effect before the actual priority has been lowered.
R Z25. Disabling a Local APIC Disables Both Logical Processor APICs on a HyperThreading Technology Enabled Processor Problem: Disabling a local APIC on one logical processor of a Hyper-Threading Technology enabled processor by clearing bit 11 of the IA32_APIC_BASE MSR will effectively disable the local APIC on the other logical processor. Implication: Disabling a local APIC on one logical processor prevents the other logical processor from sending or receiving interrupts.
R Z28. Changes to CR3 Register do not Fence Pending Instruction Page Walks Problem: When software writes to the CR3 register, it is expected that all previous/outstanding code, data accesses and page walks are completed using the previous value in CR3 register. Due to this erratum, it is possible that a pending instruction page walk is still in progress, resulting in an access (to the PDE portion of the page table) that may be directed to an incorrect memory address.
R Z30. System Bus Interrupt Messages without Data that Receive a HardFailure Response May Hang the Processor Problem: When a system bus agent (processor or chipset) issues an interrupt transaction without data onto the system bus and the transaction receives a HardFailure response, a potential processor hang can occur.
R Z33. A 16-bit Address Wrap Resulting from a Near Branch (Jump or Call) May Cause an Incorrect Address to Be Reported to the #GP Exception Handler Problem: If a 16-bit application executes a branch instruction that causes an address wrap to a target address outside of the code segment, the address of the branch instruction should be provided to the general protection exception handler.
R Z36. xAPIC May Not Report Some Illegal Vector Errors Problem: The local xAPIC has an Error Status Register, which records all errors. The bit 6 (the Receive Illegal Vector bit) of this register, is set when the local xAPIC detects an illegal vector in a received message. When an illegal vector error is received on the same internal clock that the error status register is being written (due to a previous error), bit 6 does not get set and illegal vector errors are not flagged.
R Z39. A Timing Marginality in the Instruction Decoder Unit May Cause an Unpredictable Application Behavior and/or System Hang Problem: A timing marginality may exist in the clocking of the instruction decoder unit which leads to a circuit slowdown in the read path from the Instruction Decode PLA circuit. This timing marginality may not be visible for some period of time.
R Z42. With TF (Trap Flag) Asserted, FP Instruction That Triggers an Unmasked FP Exception May Take Single Step Trap Before Retirement of Instruction Problem: If an FP instruction generates an unmasked exception with the EFLAGS.TF=1, it is possible for external events to occur, including a transition to a lower power state. When resuming from the lower power state, it may be possible to take the single step trap before the execution of the original FP instruction completes.
R Workaround: 1. The central agent can issue a bus cycle that causes a cache line to be invalidated (Bus Read Invalidate Line (BRIL) or BWIL transaction) in response to a processor-generated BWIL (or BLW) transaction to insure complete invalidation of the associated cache line. If there are no intervening processororiginated transactions to that cache line, the central agent’s invalidating snoop will get a clean snoop result. Or 2. Snoop filtering central agents can: a.
R Z47. A Write to an APIC Register Sometimes May Appear to Have Not Occurred Problem: With respect to the retirement of instructions, stores to the uncacheable memory-based APIC register space are handled in a non-synchronized way. For example if an instruction that masks the interrupt flag, e.g. CLI, is executed soon after an uncacheable write to the Task Priority Register (TPR) that lowers the APIC priority, the interrupt masking operation may take effect before the actual priority has been lowered.
R Specification Changes There are no Specification Changes in this Specifcation Update revision.
R Specification Clarifications There are no Specification Clarifications in this Specification Update revision.
R Documentation Changes There are no Documentation Changes in this Specification Update revision.
