Mobile Intel Pentium 4 Processor with 533 MHz Front Side Bus

18 Mobile Intel
®
Pentium
®
4 Processor with 533 MHz System Bus Datasheet
Electrical Specifications
2.5 Signal Terminations, Unused Pins, and
TESTHI[10:0]
All NC pins must remain unconnected. Connection of these pins to V
CC
, V
SS
, or to any other signal
(including each other) can result in component malfunction or incompatibility with future mobile
Intel Pentium 4 processors. See Section 5.2 for a pin listing of the processor and the location of all
NC pins.
For reliable operation, always connect unused inputs or bidirectional signals that are not terminated
on the die to an appropriate signal level. Note that on-die termination has been included on the
mobile Intel Pentium 4 processor to allow signals to be terminated within the processor silicon.
Unused active low GTL+ inputs may be left as no connects if GTL+ termination is provided on the
processor silicon. Table 4 lists details on GTL+ signals that do not include on-die termination.
Unused active high inputs should be connected through a resistor to ground (V
SS
). Refer to the
platform design guidelines listed in Table 1 for the appropriate resistor values.
Unused outputs can be left unconnected, however, this may interfere with some TAP functions,
complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying
bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability. For unused GTL+ input or I/O signals that don’t have on-die
termination, use pull-up resistors of the same value in place of the on-die termination resistors
(R
TT
). See Table 16.
The TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die
termination. Inputs and used outputs must be terminated on the system board. Unused outputs may
be terminated on the system board or left unconnected. Note that leaving unused outputs
unterminated may interfere with some TAP functions, complicate debug probing, and prevent
boundary scan testing. Signal termination for these signal types is discussed in the appropriate
platform design guidelines listed in Table 1. TAP signal termination requirements are also
discussed in ITP700 Debug Port Design Guide.
The TESTHI pins should be tied to the processor V
CC
using a matched resistor, where a matched
resistor has a resistance value within +
20% of the impedance of the board transmission line traces.
For example, if the trace impedance is 50
Ω, then a value between 40 Ω and 60 Ω is required.
The TESTHI pins may use individual pull-up resistors or be grouped together as detailed below. A
matched resistor should be used for each group:
1. TESTHI[1:0]
2. TESTHI[5:2]
3. TESTHI[10:8]
Additionally, if the ITPCLKOUT[1:0] pins are not used then they may be connected individually to
V
CC
using matched resistors or grouped with TESTHI[5:2] with a single matched resistor. If they
are being used, individual termination with 1-k
Ω resistors is required. Tying ITPCLKOUT[1:0]
directly to V
CC
or sharing a pull-up resistor to V
CC
will prevent use of debug interposers. This
implementation is strongly discouraged for system boards that do not implement an onboard debug
port.