Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology on 90-nm Process Technology

Mobile Intel® Pentium® 4 Processor Supporting Hyper-Threading Technology on 90-nm Process Technology Datasheet 11

Electrical Specifications

2 Electrical Specifications

2.1 Power and Ground Pins

For clean on-chip power distribution, the processor has 85 V

(power) and 179 V

(ground) pins.

All power pins must be connected to V

, while all V

pins must be connected to a system ground

plane.The processor V

pins must be supplied the voltage determined by the VID (Voltage

identification) pins.

2.2 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of

generating large current swings between low and full power states. This may cause voltages on

power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be

taken in the board design to ensure that the voltage provided to the processor remains within the

specifications listed in Table 2-8. Failure to do so can result in timing violations or reduced lifetime

of the component. For further information and design guidelines, refer to the Intel

852GME and

Intel

852PM Chipset Platforms Design Guide.

2.2.1 Vcc Decoupling

Regulator solutions need to provide bulk capacitance with a low effective series resistance (ESR)

and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the

large current swings when the part is powering on, or entering/exiting low power states, must be

provided by the voltage regulator solution (VR). For more details on this topic, refer to the Intel

852GME and Intel

852PM Chipset Platforms Design Guide.

2.2.2 Front Side Bus GTL+ Decoupling

The processor integrates signal termination on the die as well as incorporating high frequency

decoupling capacitance on the processor package. Decoupling must also be provided by the system

baseboard for proper GTL+ bus operation. For more information, refer to the Intel

852GME and

Intel

852PM Chipset Platforms Design Guide.

2.2.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the front side bus interface speed as well as the core frequency of the

processor. As in previous generation processors, the processor core frequency is a multiple of the

BCLK[1:0] frequency. No user intervention is necessary, and the processor will automatically run

at the speed indicated on the package. The processor uses a differential clocking implementation.