Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology* on 90 nm Process Technology Specification Update

28 Specification Update

will update the MCA Error Code field without updating the rest of the register, thereby leaving the

IA32_MC0_STATUS register with stale information.

• When a speculative load operation hits the L2 cache and receives a correctable error, the

IA32_MC1_Status Register may be updated with incorrect information. The IA32_MC1_Status

• The processor should only log the address for L1 parity errors in the IA32_MC1_Status register if a

valid address is available. If a valid address is not available, the Address Valid bit in the

IA32_MC1_Status register should not be set. In instances where an L1 parity error occurs and the

address is not available because the linear to physical address translation is not complete or an

internal resource conflict has occurred, the Address Valid bit is incorrectly set.

• The processor may hang when an instruction code fetch receives a hard failure response from the

system bus. This occurs because the bus control logic does not return data to the core, leaving the

processor empty. IA32_MC0_STATUS MSR does indicate that a hard fail response occurred.

• The processor may hang when the following events occur and the machine check exception is enabled,

CR4.MCE=1. A processor that has its STPCLK# pin asserted will internally enter the Stop Grant

State and finally issue a Stop Grant Acknowledge special cycle to the bus. If an uncorrectable error is

generated during the Stop Grant process it is possible for the Stop Grant special cycle to be issued to

the bus before the processor vectors to the machine check handler. Once the chipset receives its last

Stop Grant special cycle it is allowed to ignore any bus activity from the processors. As a result,

processor accesses to the machine check handler may not be acknowledged, resulting in a processor

hang.

Implication: The processor is unable to correctly report and/or recover from certain errors.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

Q35.

EFLAGS.RF May Be Incorrectly Set after an IRET Instruction

Problem: EFLAGS.RF is used to disable code breakpoints. After an IRET instruction, EFLAGS.RF may be

incorrectly set or not set depending on its value right before the IRET instruction.

Implication: A code breakpoint may be missed or an additional code breakpoint may be taken on next instruction.

Workaround: It is possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

Q36.

Writing the Echo TPR Disable Bit in IA32_MISC_ENABLE May Cause a #GP Fault

Problem: Writing a ‘1’ to the Echo TPR disable bit (bit 23) in IA32_MISC_ENABLE may incorrectly cause a

#GP fault.

Implication: A #GP fault may occur if the bit is set to a ‘1’.

Workaround: It is possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.