Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology* on 90 nm Process Technology Specification Update

R
Specification Update 19
Q10.
The Processor Signals Page-Fault Exception (#PF) Instead of Alignment Check
Exception (#AC) on an Unlocked CMPXCHG8B Instruction
Problem: If a Page-Fault Exception (#PF) and Alignment Check Exception (#AC) both occur for an unlocked
CMPXCHG8B instruction, then #PF will be flagged.
Implication: Software that depends on the Alignment Check Exception (#AC) before the Page-Fault Exception (#PF)
will be affected since #PF is signaled in this case.
Workaround: Remove the software’s dependency on #AC having precedence over #PF. Alternately, correct the page
fault in the page fault handler and then restart the faulting instruction.
Status: For the steppings affected, see the Summary Tables of Changes.
Q11.
FSW May not be Completely Restored after Page Fault on FRSTOR or FLDENV
Instructions
Problem: If the FPU operating environment or FPU state (operating environment and register stack) being loaded
by an FLDENV or FRSTOR instruction wraps around a 64-Kbyte or 4-Gbyte boundary and a page fault
(#PF) or segment limit fault (#GP or #SS) occurs on the instruction near the wrap boundary, the upper
byte of the FPU status word (FSW) might not be restored. If the fault handler does not restart program
execution at the faulting instruction, stale data may exist in the FSW.
Implication: When this erratum occurs, stale data will exist in the FSW.
Workaround: Ensure that the FPU operating environment and FPU state do not cross 64-Kbyte or 4-Gbyte boundaries.
Alternately, ensure that the page fault handler restarts program execution at the faulting instruction after
correcting the paging problem.
Status: For the steppings affected, see the Summary Tables of Changes.
Q12.
Processor Issues Inconsistent Transaction Size Attributes for Locked Operation
Problem: When the processor is in the Page Address Extension (PAE) mode and detects the need to set the Access
and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte load lock onto
the System Bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte store unlock occurs.
Correct data is provided since only the lower bytes change, however external logic monitoring the data
transfer may be expecting an 8-byte store unlock.
Implication: No known commercially available chipsets are affected by this erratum.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.