Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology* on 90 nm Process Technology Specification Update

R
14 Specification Update
Errata
Q1. Transaction Is Not Retired after BINIT#
Problem: If the first transaction of a locked sequence receives a HITM# and DEFER# during the snoop phase it
should be retried and the locked sequence restarted. However, if BINIT# is also asserted during this
transaction, the transaction will not be retried.
Implication: When this erratum occurs, locked transactions will not be retried.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
Q2.
Invalid Opcode 0FFFh Requires a ModRM Byte
Problem: Some invalid opcodes require a ModRM byte and other following bytes, while others do not. The invalid
opcode 0FFFh did not require a ModRM in previous generation microprocessors such as Pentium II or
Pentium III processors, but it is required in the Intel Pentium 4 processors and the Mobile Intel
®
Pentium
®
4 processor supporting Hyper-Threading Technology on 90-nm technology process processor
Implication: The use of an invalid opcode 0FFFh without the ModRM byte may result in a page or limit fault on the
Prescott processor. When this erratum occurs, locked transactions will not be retried.
Workaround: To avoid this erratum use ModRM byte with invalid 0FFFh opcode.
Status: For the steppings affected, see the Summary Tables of Changes.
Q3.
Processor May Hang Due to Speculative Page Walks to Nonexistent System
Memory
Problem: A load operation issued speculatively by the processor that misses the Data Translation Lookaside
Buffer (DTLB) results in a page walk. A branch instruction older than the load retires so that this load
operation is now in the mispredicted branch path. Due to an internal boundary condition, in some
instances the load is not canceled before the page walk is issued.
The Page Miss Handler (PMH) starts a speculative page-walk for the Load and issues a cacheable load
of the Page Directory Entry (PDE). This PDE load returns data that points to a page table entry in
uncacheable (UC) memory. The PMH issues the PTE Load to UC space, which is issued on the Front
Side Bus. No response comes back for this load PTE operation since the address is pointing to system
memory, which does not exist.
This load to non-existent system memory causes the processor to hang because other bus requests are
queued up behind this UC PTE load, which never gets a response. If the load was accessing valid system
memory, the speculative page-walk would successfully complete and the processor would continue to
make forward progress.