R Mobile Intel® Pentium® 4 Processor Supporting Hyper-Threading Technology† on 90 nm Process Technology Specification Update January 2006 Notice: The Mobile Intel® Pentium® 4 Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
R INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
R Contents Revision History ............................................................................................................................4 Preface ..........................................................................................................................................5 Summary Tables of Changes........................................................................................................7 Identification Information ...................................................
R Revision History Rev.
R Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
R Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics, e.g., core speed, L2 cache size, package type, etc. as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number Errata are design defects or errors. Errata may cause the Mobile Intel® Pentium® 4 Processor’s behavior to deviate from published specifications.
R Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes which apply to the listed Mobile Intel® Pentium® 4 Processor supporting Hyper-Threading Technology on 90-nm process technology steppings. Intel intends to fix some of the errata in a future stepping of the component and to account for the other outstanding issues through documentation or Specification Changes as noted.
R ® ® K = Mobile Intel Pentium III Processor – M ® ® L = Intel Celeron D processor ® ® M =Mobile Intel Celeron processor ® ® N = Intel Pentium 4 processor ® ® O = Intel Xeon processor MP ® ® P = Intel Xeon processor ® ® Q = Mobile Intel Pentium 4 processor supporting Hyper-Threading Technology on 90-nm technology process R = Intel® Pentium® 4 processor on 90 nm process ® S = 64-bit Intel® Xeon processor with 800 MHz system bus (1-MB and 2-MB L2 cache versions) ® ® ® ® T = Mobile Intel Pentium 4 proc
R NO. D0 E0 Plans Q14 X X NoFix Shutdown and IERR# may result due to a Machine Check Exception on a Hyper-Threading technology enabled processor Q15 X X NoFix Processor may hang under certain frequencies and 12.
R 10 NO.
R NO.
R Identification Information The processor can be identified by the following values: Family1 Model2 1111b 0011b NOTES: 1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan. 2.
R Component Marking Information Figure 1. Mobile Intel® Pentium® 4 Processor Supporting Hyper-Threading Technology on 90 nm Process Technology Package Markings Frequency/Cache/Bus/Voltage S-Spec/Country of Assy FPO - Serial # 2 GHZ/256/400/1.
R Errata Q1. Transaction Is Not Retired after BINIT# Problem: If the first transaction of a locked sequence receives a HITM# and DEFER# during the snoop phase it should be retried and the locked sequence restarted. However, if BINIT# is also asserted during this transaction, the transaction will not be retried. Implication: When this erratum occurs, locked transactions will not be retried. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. Q2.
R Implication: Processor may hang due to speculative page walks to non-existent system memory. Workaround: Page directories and page tables in UC memory space must point to system memory that exists. Status: For the steppings affected, see the Summary Tables of Changes. Q4.
R correct the correctable error but cannot proceed due to the uncorrectable error. When this occurs the processor will hang. When an L1 cache parity error occurs, the cache controller logic should write the physical address of the data memory location that produced that error into the IA32_MC1_ADDR REGISTER (MC1_ADDR).
R When a speculative load operation hits the L2 cache and receives a correctable error, the IA32_MC1_Status Register may be updated with incorrect information. The IA32_MC1_Status Register should not be updated for speculative loads. The processor should only log the address for L1 parity errors in the IA32_MC1_Status register if a valid address is available. If a valid address is not available, the Address Valid bit in the IA32_MC1_Status register should not be set.
R Implication: Certain debug mechanisms do not function as expected on the processor. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. Q7. Cascading Of Performance Counters Does Not Work Correctly When Forced Overflow Is Enabled Problem: The performance counters are organized into pairs. When the CASCADE bit of the Counter Configuration Control Register (CCCR) is set, a counter that overflows will continue to count in the other counter of the pair.
R Q10. The Processor Signals Page-Fault Exception (#PF) Instead of Alignment Check Exception (#AC) on an Unlocked CMPXCHG8B Instruction Problem: If a Page-Fault Exception (#PF) and Alignment Check Exception (#AC) both occur for an unlocked CMPXCHG8B instruction, then #PF will be flagged. Implication: Software that depends on the Alignment Check Exception (#AC) before the Page-Fault Exception (#PF) will be affected since #PF is signaled in this case.
R Q13. When the Processor is in the System Management Mode (SMM), Debug Registers May Be Fully Writeable Problem: When in System Management Mode (SMM), the processor executes code and stores data in the SMRAM space. When the processor is in this mode and writes are made to DR6 and DR7, the processor should block writes to the reserved bit locations. Due to this erratum, the processor may not block these writes. This may result in invalid data in the reserved bit locations.
R Q16. System May Hang if a Fatal Cache Error Causes Bus Write Line (BWL) Transaction to Occur to the Same Cache Line Address as an Outstanding Bus Read Line (BRL) or Bus Read-Invalidate Line (BRIL) Problem: A processor internal cache fatal data ECC error may cause the processor to issue a BWL transaction to the same cache line address as an outstanding BRL or BRIL.
R Q19. Parity Error in the L1 Cache May Cause the Processor to Hang Problem: If a locked operation accesses a line in the L1 cache that has a parity error, it is possible that the processor may hang while trying to evict the line. Implication: If this erratum occurs, it may result in a system hang. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. Q20.
R Q22. Some Front Side Bus I/O Specifications Are Not Met Problem: The following front side bus I/O specifications are not met: • The VIH(min) for the GTL+ signals is specified as GTLREF + (0.10 * VCC) [V]. • The VIH(min) for the Asynchronous GTL+ signals is specified as Vcc/2 + (0.10 * VCC) [V]. • Common Clock Output Valid Delay(min) is specified as -0.250 ns. • Common Clock Input Setup Time is specified as 0.700 ns. • Source Synchronous Input Setup Time to Strobe is specified as 0.150 ns.
R Q25. xAPIC May Not Report Some Illegal Vector Errors Problem: The local xAPIC has an Error Status Register, which records all errors. The bit 6 (the Receive Illegal Vector bit) of this register, is set when the local xAPIC detects an illegal vector in a received message. When an illegal vector error is received on the same internal clock that the error status register is being written (due to a previous error), bit 6 does not get set and illegal vector errors are not flagged.
R Q28. Enabling No-Eviction Mode (NEM) May Prevent the Operation of the Second Logical Processor in a Hyper-Threading Technology Enabled Processor Problem: In an HT Technology enabled system, when NEM is enabled by setting Bit 0 of MSR 080h (IA32_BIOS_CACHE_AS_RAM), the second logical processor may fail to wake up from "Wait-forSIPI" state. Implication: In an HT Technology enabled system, the second logical processor may not respond to SIPI.
R Q32. Using STPCLK and Executing Code from Very Slow Memory Could Lead to a System Hang Problem: The system may hang when the following conditions are met: 1. Periodic STPCLK mechanism is enabled via the chipset 2. Hyper-Threading Technology is enabled 3. One logical processor is waiting for an event (i.e. hardware interrupt) 4. The other logical processor executes code from very slow memory such that every code fetch is deferred long enough for the STPCLK to be re-asserted.
R • When the reporting of errors is disabled for Machine Check Architecture (MCA) Bank 2 by setting all MC2_CTL register bits to 0, uncorrectable errors should be logged in the IA32_MC2_STATUS register but no machine-check exception should be generated. Uncorrectable loads on bank 2, which would normally be logged in the IA32_MC2_STATUS register, are not logged.
R will update the MCA Error Code field without updating the rest of the register, thereby leaving the IA32_MC0_STATUS register with stale information. • When a speculative load operation hits the L2 cache and receives a correctable error, the IA32_MC1_Status Register may be updated with incorrect information. The IA32_MC1_Status Register should not be updated for speculative loads.
R Q37. Incorrect Access Controls to MSR_LASTBRANCH_0_FROM_LIP MSR Registers Problem: When an access is made to the MSR_LASTBRANCH_0_FROM_LIP MSR register, an expected #GP fault may not happen. Implication: A read of the MSR_LASTBRANCH_0_FROM_LIP MSR register may not cause a #GP fault. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. Q38.
R Q41. Machine Check Exceptions May Not Update Last-Exception Record MSRs (LERs) Problem: The Last-Exception Record MSRs (LERs) may not get updated when Machine Check Exceptions occur. Implication: When this erratum occurs, the LER may not contain information relating to the machine check exception. They will contain information relating to the exception prior to the machine check exception. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. Q42.
R Q45. Execution of IRET or INTn Instructions May Cause Unexpected System Behavior Problem: There is a small window of time, requiring alignment of many internal micro architectural events, during which the speculative execution of the IRET or INTn instructions in protected or IA-32e mode may result in unexpected software or system behavior. Implication: This erratum may result in unexpected instruction execution, events, interrupts or a system hang when the IRET instruction is executed.
R Q48. With TF (Trap Flag) Asserted, FP Instruction That Triggers an Unmasked FP Exception May Take Single Step Trap Before Retirement of Instruction Problem: If an FP instruction generates an unmasked exception with the EFLAGS.TF=1, it is possible for external events to occur, including a transition to a lower power state. When resuming from the lower power state, it may be possible to take the single step trap before the execution of the original FP instruction completes.
R Q51. Processor May Hang When Resuming from Deep Sleep State Problem: When resuming from the Deep Sleep state, the IO Phase Lock Loop (IOPLL) may not properly lock. Implication: When this erratum occurs, the processor may hang. Workaround: The system BIOS should prevent the processor from going to the Deep Sleep state. Status: For the steppings affected, see the Summary Tables of Changes. Q52.
R Q54. TPR (Task Priority Register) Updates during Voltage Transitions of Power Management Events May Cause a System Hang Problem: Systems with Echo TPR Disable (R/W) bit (bit [23] of IA32_MISC_ENABLE register) set to '0' (default), where xTPR messages are being transmitted on the system bus to the processor, may experience a system hang during voltage transitions caused by the power management events. Implication: This may cause a system hang during voltage transitions of power management events.
R Q57. It Is Possible That Two Specific Invalid Opcodes May Cause Unexpected Memory Accesses Problem: A processor is expected to respond with an undefined opcode (#UD) fault when executing either opcode 0F 78 or a Grp 6 Opcode with bits 5:3 of the Mod/RM field set to 6, however the processor may respond instead, with a load to an incorrect address. Implication: This erratum may cause unpredictable system behavior or system hang.
R Q60. Front Side Bus Machine Checks May be Reported as a Result of On-Going Transactions during Warm Reset Problem: Processor Front Side Bus (FSB) protocol/signal integrity machine checks may be reported if the transactions are initiated or in-progress during a warm reset. A warm reset is where the chipset asserts RESET# when the system is running. Implication: The processor may log FSB protocol/signal integrity machine checks if transactions are allowed to occur during RESET# assertions.
R Q63. A Write to an APIC Register Sometimes May Appear to Have Not Occurred Problem: With respect to the retirement of instructions, stores to the uncacheable memory-based APIC register space are handled in a non-synchronized way. For example if an instruction that masks the interrupt flag, e.g. CLI, is executed soon after an uncacheable write to the Task Priority Register (TPR) that lowers the APIC priority, the interrupt masking operation may take effect before the actual priority has been lowered.
R Specification Changes The Specification Changes listed in this section apply to the following documents: • Mobile Intel® Pentium® 4 Processor supporting Hyper-Threading Technology on 90-nm process technology Datasheet All Specification Changes will be incorporated into a future version of the appropriate Mobile Pentium 4 Processor supporting Hyper-Threading Technology on 90-nm process technology documentation. Q1.
R Specification Clarifications All Specification Clarifications will be incorporated into a future version of the appropriate Mobile Pentium 4 processor documentation. Q1. Removed See the Revision History for details. Q2.
R Documentation Changes The Documentation Changes listed in this section apply to the following documents: • Mobile Intel® Pentium® 4 Processor supporting Hyper-Threading Technology on 90-nm process technology Datasheet All Documentation Changes will be incorporated into a future version of the appropriate Mobile Pentium 4 processor documentation.
