Mobile Intel Pentium 4 Processor with 533 MHz Front Side Bus

Mobile Intel
®
Pentium
®
4 Processor with 533 MHz System Bus Datasheet 21
Electrical Specifications
2.7 Asynchronous GTL+ Signals
Mobile Intel Pentium 4 processor does not utilize CMOS voltage levels on any signals that connect
to the processor. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0/INTR,
LINT1/NMI, SMI#, SLP#, and STPCLK# use GTL+ input buffers. Legacy output FERR#/PBE#
and other non-GTL+ signals (THERMTRIP#) utilize GTL+ output buffers. PROCHOT# uses
GTL+ input/output buffer. All of these signals follow the same DC requirements as GTL+ signals,
however the outputs are not actively driven high (during a logical 0 to 1 transition) by the
processor. These signals do not have setup or hold time specifications in relation to BCLK[1:0].
However, all of the Asynchronous GTL+ signals are required to be asserted for at least two BCLKs
in order for the processor to recognize them. See Section 2.11 for the DC and AC specifications for
the Asynchronous GTL+ signal groups. See Section 6.2 for additional timing requirements for
entering and leaving the low power states.
2.8 Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is
recommended that the mobile Intel Pentium 4 processor be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to connect to the rest
of the chain unless one of the other components is capable of accepting an input of the appropriate
voltage level. Similar considerations must be made for TCK, TMS, and TRST#. Two copies of
each signal may be required, with each driving a different voltage level. Refer to ITP700 Debug
Port Design Guide for more detailed information.
2.9 FSB Frequency Select Signals (BSEL[1:0])
The BSEL[1:0] are output signals used to select the frequency of the processor input clock
(BCLK[1:0]). Table 5 defines the possible combinations of the signals and the frequency
associated with each combination. The required frequency is determined by the processor, chipset,
and clock synthesizer. All agents must operate at the same frequency.
The mobile Intel Pentium 4 processor with 533 MHz FSB currently operates at a 533-MHz FSB
frequency (selected by a 133-MHz BCLK[1:0] frequency). Individual processors will only operate
at their specified FSB frequency.
For more information about these pins refer to Section 4.2 and the appropriate platform design
guidelines.
Table 5. BSEL[1:0] Frequency Table for BCLK[1:0]
BSEL1 BSEL0 Function
L L RESERVED
L H 133 MHz
H L RESERVED
H H RESERVED