Mobile Intel Pentium 4 Processor with 533 MHz Front Side Bus

10 Mobile Intel
®
Pentium
®
4 Processor with 533 MHz System Bus Datasheet
Introduction
The processor’s 533 MHz Intel NetBurst micro-architecture FSB utilizes a split-transaction,
deferred reply protocol like the Intel Pentium 4 processor. This FSB is not compatible with the P6
processor family bus. The 533-MHz Intel NetBurst micro-architecture FSB uses Source-
Synchronous Transfer (SST) of address and data to improve performance by transferring data four
times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address
bus can deliver addresses two times per bus clock and is referred to as a “double-clocked” or 2X
address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth
of up to 4.3 Gbytes/second.
The processor, when used in conjunction with the requisite Intel SpeedStep

technology applet or
its equivalent, supports Enhanced Intel SpeedStep technology, which enables real-time dynamic
switching of the voltage and frequency between two performance modes. This occurs by switching
the bus ratios, core operating voltage, and core processor speeds without resetting the system.
The processor FSB uses GTL+ signalling technology. The mobile Intel Pentium 4 processor with
533 MHz FSB is expected to be available at the following core frequencies:
• 3.20 GHz (in Maximum Performance Mode at 1.55 V). This processor runs at 1.60 GHz (in
Battery Optimized Mode at 1.20 V
• 3.06 GHz (in Maximum Performance Mode at 1.55 V). This processor runs at 1.60 GHz (in
Battery Optimized Mode at 1.20 V)
• 2.80 GHz (in Maximum Performance Mode at 1.525 V). This processor runs at 1.60 GHz (in
Battery Optimized Mode at 1.20 V)
• 2.66 GHz (in Maximum Performance Mode at 1.525 V). This processor runs at 1.60 GHz (in
Battery Optimized Mode at 1.20 V)
• 2.40 GHz (in Maximum Performance Mode at 1.525 V). This processor runs at 1.60 GHz (in
Battery Optimized Mode at 1.20 V)
1.1 Terminology
A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a
hex “A”, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic
level).
“Front Side Bus (FSB)” refers to the interface between the processor and system core logic (a.k.a.
the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O.
Commonly used terms are explained here for clarification:
• Processor — For this document, the term processor shall mean the mobile Intel Pentium 4
processor with 533 MHz FSB in the 478-pin package.
• Keep out zone — The area on or near the processor that system design can not utilize.
• Intel 852 GME/PM chipsets — Mobile chipset that will support the mobile Intel
Pentium 4 processor with 533 MHz FSB.
• Processor core — Mobile Intel Pentium 4 processor with 533 MHz FSB core die with
integrated L2 cache.