Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology on 90-nm Process Technology

Mobile Intel® Pentium® 4 Processor Supporting Hyper-Threading Technology on 90-nm Process Technology Datasheet 71
Features
— If the target frequency is higher than the current frequency, Vcc is ramped up in
incremental steps (+12.5 mV VID step) by placing a new value on the VID signals and the
PLL then locks to the new frequency. Note that the top frequency for the processor can not
be exceeded.
— If the target frequency is lower than the current frequency, the PLL locks to the new
frequency and then Vcc is ramped down in decremental steps (-12.5 mV VID step) by
changing the target VID through the VID signals.
• The processor will control voltage ramp rates internally to ensure glitch free transitions.
• Low transition latency and large number of transitions possible per second.
— Processor core (including L2 cache) are unavailable for up to 10
µs during the frequency
transition
— The bus protocol (BNR# mechanism) is used to block snooping
• No bus master arbiter disable required prior to transition and no processor cache flush
necessary.
§