Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology on 90-nm Process Technology

70 Mobile Intel® Pentium® 4 Processor Supporting Hyper-Threading Technology on 90-nm Process Technology Datasheet
Features
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP#
and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the reset sequence.
While in the Sleep state, the processor is capable of entering an even lower power state, the Deep
Sleep state, by asserting the DPSLP# pin (See Section 6.2.6). Once in the Sleep or Deep Sleep
state, the SLP# pin must be de-asserted if another asynchronous front side bus event needs to occur.
The SLP# pin has a minimum assertion of one BCLK period.
When the processor is in the Sleep state, it will not respond to interrupts or snoop transactions.
6.2.6 Deep Sleep State—State 6
Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep
Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. The DPSLP# pin must
be de-asserted to re-enter the Sleep state. A period of 30 microseconds (to allow for PLL
stabilization) must occur before the processor can be considered to be in the Sleep State. Once in
the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state.
The clock may be stopped when the processor is in the Deep Sleep state in order to support the
ACPI S1 state. The clock may only be stopped after DPSLP# is asserted and must be restarted
before DPSLP# is deasserted. To provide maximum power conservation when stopping the clock
during Deep Sleep, hold the BCLK0 input at V
OL
and the BCLK1 input at V
OH
.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions of signals are allowed on the front side bus while the
processor is in Deep Sleep state. Any transition on an input signal before the processor has returned
to Stop-Grant state will result in unpredictable behaviour.
6.2.7 Deeper Sleep State—State 7
The Deeper Sleep State is the lowest power state the processor can enter. This state is functionally
identical to the Deep Sleep state but at a lower core voltage. The control signals to the voltage
regulator to initiate a transition to the Deeper Sleep state are provided on the platform. Please refer
the Intel® 852GME and Intel® 852PM Chipset Platforms Design Guide for details.
6.3 Enhanced Intel SpeedStep
®
Technology
The processor will feature Enhanced Intel SpeedStep technology. Unlike previous implementations
of Intel SpeedStep technology, this technology will enable the processor to switch between
multiple voltage and operating frequency points instead of two. This will enable superior
performance with optimal power savings. Switching between states will be software controlled
unlike previous generation processor implementations where the GHI# pin was used to toggle
between two states. Following are the key features of Enhanced Intel SpeedStep technology:
• Multiple voltage/frequency operating points provide optimal performance at the lowest power.
• Voltage/Frequency selection will be software controlled by writing to processor MSRs (Model
Specific Registers) thus eliminating chipset dependency.