Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology on 90-nm Process Technology

Mobile Intel® Pentium® 4 Processor Supporting Hyper-Threading Technology on 90-nm Process Technology Datasheet 17
Electrical Specifications
NOTES:
1. Signals that do not have R
TT
, nor are actively driven to their high-voltage level.
2. The OPTIMIZED/COMPAT# and BOOTSELECT pins have a 500-5000 Ω pullup to VCCVID rather than R
TT
.
NOTE: These signals also have hysteresis added to the reference voltage. See Table 2-12 for more
information.
2.6 Asynchronous GTL+ Signals
Legacy input signals such as A20M#, DPSLP#, IGNNE#, INIT#, SMI#, SLP#, and STPCLK#
utilize CMOS input buffers. All of these signals follow the same DC requirements as GTL+
signals, however the outputs are not actively driven high (during a logical 0 to 1 transition) by the
processor. These signals do not have setup or hold time specifications in relation to BCLK[1:0].
2.7 Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is
recommended that the processor be first in the TAP chain and followed by any other components
within the system. A translation buffer should be used to connect to the rest of the chain unless one
of the other components is capable of accepting an input of the appropriate voltage level. Similar
considerations must be made for TCK, TMS, TRST#, TDI, and TDO. Two copies of each signal
may be required, with each driving a different voltage level.
Table 2-4. Signal Description Table
Signals with R
TT
Signals with no R
TT
A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,
BNR#, BOOTSELECT
2
, BPRI#, D[63:0]#, DBI[3:0]#,
DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,
OPTIMIZED/COMPAT#
2
, PROCHOT#, REQ[4:0]#,
RS[2:0]#, RSP#, TRDY#
A20M#, BCLK[1:0], BPM[5:0]#, BR0#, BSEL[1:0],
COMP[1:0], DPSLP#, FERR#/PBE#, IERR#,
IGNNE#, INIT#, LINT0/INTR, LINT1/NMI,
PWRGOOD, RESET#, SKTOCC#, SLP#, SMI#,
STPCLK#, TDO, TESTHI[11:0], THERMDA,
THERMDC, THERMTRIP#, VID[5:0], VIDPWRGD,
GTLREF[3:0], TCK, TDI, TRST#, TMS
Open Drain Signals
1
BSEL[1:0], VID[5:0], THERMTRIP#, FERR#/PBE#,
IERR#, BPM[5:0]#, BR0#, TDO
Table 2-5. Signal Reference Voltages
GTLREF V
CC
/2 VCCVID/2
BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#, BINIT#,
BNR#, HIT#, HITM#, MCERR#, PROCHOT#, BR0#,
A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BPRI#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#,
DSTBN[3:0]#, DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,
RSP#, TRDY#
A20M#, DPSLP#, IGNNE#,
INIT#, PWRGOOD
1
, SLP#,
SMI#, STPCLK#, TCK
1
,
TDI
1
, TMS
1
, TRST#
1
VIDPWRGD,
BOOTSELECT,
OPTIMIZED/
COMPAT#