Mobile Intel® Pentium® 4 Processor Supporting Hyper-Threading Technology on 90-nm Process Technology Datasheet January 2005 Document Number: 302424-003
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Contents 1 Introduction......................................................................................................................... 7 1.1 1.2 2 Electrical Specifications.................................................................................................... 11 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 3 Package Mechanical Specifications .................................................................... 27 3.1.1 Package Mechanical Drawing ..................................
5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 6 Features ........................................................................................................................... 67 6.1 6.2 6.3 7 Power-On Configuration Options ........................................................................ 67 Clock Control and Low Power States.................................................................. 67 6.2.1 Normal State—State 1 ........................................................................... 67 6.2.
Figures 2-1 2-2 2-3 3-1 3-2 3-3 3-4 3-5 4-1 4-2 5-1 5-2 6-1 Phase Lock Loop (PLL) Filter Requirements ...................................................... 14 Vcc Static and Transient Tolerance1, 2, 3 .......................................................... 22 VCC Overshoot Example Waveform................................................................... 26 Processor Package Assembly Sketch.................................................................27 Processor Package Drawing Sheet 1 of 2.......
Revision History Revision Number 001 002 003 Description Date • Initial release June 2004 • Added Mobile Intel® Pentium® 4 Processor 548 specifications (3.33 GHz) • Updated references table • Added Mobile Intel® Pentium® 4 Processor 552 specifications (3.
Introduction 1 Introduction The Mobile Intel® Pentium® 4 processor supporting Hyper-Threading Technology on 90-nm process technology is a follow on to the Mobile Intel Pentium 4 processor on 130-nm process technology in the 478-pin package with enhancements to the Intel NetBurst® microarchitecture. The processor utilizes Flip-Chip Pin Grid Array (FC-mPGA4) package technology, and plugs into a zero insertion force (ZIF) socket.
Introduction 1.1 Terminology A # symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the # symbol implies that the signal is inverted.
Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document: Table 1-1.
Introduction 10 Mobile Intel® Pentium® 4 Processor Supporting Hyper-Threading Technology on 90-nm Process Technology Datasheet
Electrical Specifications 2 Electrical Specifications 2.1 Power and Ground Pins For clean on-chip power distribution, the processor has 85 VCC (power) and 179 VSS (ground) pins. All power pins must be connected to VCC, while all VSS pins must be connected to a system ground plane.The processor VCC pins must be supplied the voltage determined by the VID (Voltage identification) pins. 2.
Electrical Specifications Table 2-1. Core Frequency to Front Side Bus Multiplier Configuration Multiplication of System Core Frequency to Front Side Bus Frequency Core Frequency (133 MHz BCLK/533 MHz FSB) 1/14 1.86 GHz 1/15 2.00 GHz 1/16 2.13 GHz 1/17 2.26 GHz 1/18 2.40 GHz 1/19 2.53 GHz 1/20 2.66 GHz 1/21 2.80 GHz 1/22 2.93 GHz 1/23 3.06 GHz 1/24 3.20 GHz 1/25 3.33 GHz 1/26 3.46 GHz 1/27 3.60 GHz NOTE: Individual processors operate only at or below the rated frequency. 2.
Electrical Specifications Table 2-2. Voltage Identification Definition VID5 VID4 VID3 VID2 VID1 VID0 VID VID5 VID4 VID3 VID2 VID1 VID0 VID 0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.2125 1 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.2250 0 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.2375 1 0 1 0 0 0 0.8750 1 1 1 0 0 0 1.2500 0 0 1 0 0 0 0.8875 0 1 1 0 0 0 1.2625 1 0 0 1 1 1 0.9000 1 1 0 1 1 1 1.2750 0 0 0 1 1 1 0.9125 0 1 0 1 1 1 1.
Electrical Specifications 2.3.1 Phase Lock Loop (PLL) Power and Filter VCCA and VCCIOPLL are power sources required by the PLL clock generators on the processor silicon. Since these PLLs are analog in nature, they require low noise power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e., maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VCC.
Electrical Specifications 2.4 Reserved, Unused, and TESTHI Pins All RESERVED pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a pin listing of the processor and the location of all RESERVED pins. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level.
Electrical Specifications With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.
Electrical Specifications Table 2-4.
Electrical Specifications 2.8 Front Side Bus Frequency Select Signals (BSEL[1:0]) The BSEL[1:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 2-6 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency.
Electrical Specifications Table 2-7. Absolute Maximum and Minimum Ratings Symbol Parameter Min Max Unit Notes VCC Any processor supply voltage with respect to VSS - 0.3 1.55 V 1, 2 TC Processor case temperature See Section 5 See Section 5 °C 3, 4 TSTORAGE Processor storage temperature –10 +45 °C 3, 4, 5 NOTES: 1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied. 2.
Electrical Specifications Table 2-8. Voltage and Current Specifications Symbol Parameter Min HFM VID VID range for HFM (Highest Frequency Mode) 1.250 LFM VID VID for LFM (Lowest Frequency Mode) N/A VID Transition VID step size during a transition N/A VCC VCC for FMS0.5 processors Processor Number Typ Notes2 Max Unit 1.400 V 1.150 N/A V N/A ± 12.5 mV VID - ICC(max) * 1.
Electrical Specifications 3. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.3 and Table 2-2 for more information. 4. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE pins at the socket with a 100MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm.
Electrical Specifications Table 2-9. VCC Core Deep Sleep State Voltage Regulator Static and Transient Tolerance (Deep Sleep VID Offset = 1.7%) Voltage Deviation from (VID Setting - 1.7% of VID Setting) (V)1,2,3,4 Icc (A) Maximum Typical Minimum 0 0.000 -0.025 -0.050 5 -0.007 -0.033 -0.059 10 -0.015 -0.041 -0.068 15 -0.022 -0.049 -0.077 20 -0.029 -0.058 -0.086 25 -0.036 -0.066 -0.095 30 -0.044 -0.074 -0.104 35 -0.051 -0.082 -0.113 40 -0.058 -0.090 -0.122 NOTES: 1.
Electrical Specifications 3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE pins. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. Table 2-10. GTL+ Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 VIL Input Low Voltage 0.0 GTLREF - (0.10 * VCC) V 2, 6 VIH Input High Voltage GTLREF + (0.10 * VCC) VCC V 3, 4, 6 VOH Output High Voltage 0.
Electrical Specifications . Table 2-12. PWRGOOD and TAP Signal Group DC Specifications Parameter Min Max Unit Notes1, 2 VHYS Input Hysteresis 200 350 mV 7 VT+ Input low to high threshold voltage 0.5 * (VCC + VHYS_MIN) 0.5 * (VCC + VHYS_MAX) V 5 VT- Input high to low threshold voltage 0.5 * (VCC - VHYS_MAX) 0.
Electrical Specifications Table 2-15. BSEL [1:0] and VID[5:0] DC Specifications Symbol Parameter Max Unit Notes1 RON (BSEL) Buffer On Resistance 60 Ω 2 RON (VID) Buffer On Resistance 60 Ω 2 IOL Max Pin Current 8 mA ILO Output Leakage Current 200 µA VTOL Voltage Tolerance 3.3 + 5% V 3 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. These parameters are not tested and are based on design simulations. 3.
Electrical Specifications Figure 2-3. VCC Overshoot Example Waveform Example Overshoot Waveform Voltage (V) VID + 0.050 VOS VID TOS Time TOS: Overshoot time above VID VOS: Overshoot above VID NOTES: 1. Vos is measured overshoot voltage. 2. Tos is measured time duration above VID. 2.11.1 Die Voltage Validation Overshoot events from application testing on real processors must meet the specifications in Table 2-17 when measured across the VCC_SENSE and VSS_SENSE pins.
Package Mechanical Specifications 3 Package Mechanical Specifications 3.1 Package Mechanical Specifications The Mobile processor is packaged in a Flip-Chip Pin Grid Array (FC-mPGA4) package that interfaces with the motherboard via a mPGA479 socket. The package consists of a processor core mounted on a substrate pin carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications 3.1.1 Package Mechanical Drawing The package mechanical drawings are shown in Figure 3-2 and Figure 3-3. The drawings include dimensions necessary to design a thermal solution for the processor. These dimensions include: 1. Package reference with tolerances (total height, length, width, etc.) 2. IHS parallelism and tilt 3. Pin dimensions 4. Top-side and back-side component keep-out dimensions 5. Reference datums All drawing dimensions are in mm [in].
Package Mechanical Specifications Figure 3-2.
Package Mechanical Specifications Figure 3-3.
Package Mechanical Specifications 3.1.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep-out zone requirements. A thermal and mechanical solution design must not intrude into the required keepout zones. Decoupling capacitors are typically mounted to either the topside or pin-side of the package substrate. See Figure 3-2 and Figure 3-3 for keep-out zones.
Package Mechanical Specifications 3. A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface. 4. These guidelines are based on limited testing for design characterization. 3.1.5 Package Insertion Specifications The processor can be inserted into and removed from a mPGA479 socket 15 times. The socket should meet the mPGA479 requirements detailed in the mPGA479, mPGA478A, mPGA478B, mPGA478C, and mPGA476 Socket Design Guidelines. 3.1.
Package Mechanical Specifications 3.1.9 Processor Pin-Out Coordinates Figure 3-5 shows the top view of the processor pin coordinates. The coordinates are referred to throughout the document to identify processor pins. Figure 3-5.
Package Mechanical Specifications 34 Mobile Intel® Pentium® 4 Processor Supporting Hyper-Threading Technology on 90-nm Process Technology Datasheet
Pin Listing and Signal Descriptions 4 Pin Listing and Signal Descriptions 4.1 Processor Pin Assignments This chapter provides the processor pinout and signal description. Table 4-1 provides the pinout arranged alphabetically by signal name and Table 4-2 provides the pinout arranged numerically by pin number. The pinout footprint is shown in Figure 4-1 and Figure 4-2. Table 4-1.
Pin Listing and Signal Descriptions Pin Name Pin Number Signal Buffer Type Direction Pin Name Pin Number Signal Buffer Type Direction D0# B21 Source Synch Input/Output D39# N25 Source Synch Input/Output D01# B22 Source Synch Input/Output D40# R21 Source Synch Input/Output D02# A23 Source Synch Input/Output D41# P24 Source Synch Input/Output D03# A25 Source Synch Input/Output D42# R25 Source Synch Input/Output D04# C21 Source Synch Input/Output D43# R24 Source S
Pin Listing and Signal Descriptions Pin Name Pin Number Signal Buffer Type Direction Pin Name Pin Number Signal Buffer Type Direction DSTBN2# R22 Source Synch Input/Output RS2# F4 Common Clock Input DSTBN3# W22 Source Synch Input/Output RSP# AB2 Common Clock Input DSTBP0# F21 Source Synch Input/Output SKTOCC# AF26 Power/Other Output DSTBP1# J23 Source Synch Input/Output SLP# AB26 Asynch GTL+ Input DSTBP2# P23 Source Synch Input/Output SMI# B5 Asynch GTL+ Input
Pin Listing and Signal Descriptions Pin Name Pin Number Signal Buffer Type Direction Pin Name Pin Number Signal Buffer Type VCC AA18 Power/Other VCC AF9 Power/Other VCC AA8 Power/Other VCC B11 Power/Other VCC AB11 Power/Other VCC B13 Power/Other VCC AB13 Power/Other VCC B15 Power/Other VCC AB15 Power/Other VCC B17 Power/Other VCC AB17 Power/Other VCC B19 Power/Other VCC AB19 Power/Other VCC B7 Power/Other VCC AB7 Power/Other VCC B9 Power/Other VCC AB9
Pin Listing and Signal Descriptions Pin Name Pin Number Signal Buffer Type Direction Pin Name Pin Number Signal Buffer Type VCCVIDLB AF3 Power/Other Input VSS AB8 Power/Other VID0 AE5 Power/Other Output VSS AC11 Power/Other VID1 AE4 Power/Other Output VSS AC13 Power/Other VID2 AE3 Power/Other Output VSS AC15 Power/Other VID3 AE2 Power/Other Output VSS AC17 Power/Other VID4 AE1 Power/Other Output VSS AC19 Power/Other VID5 AD3 Power/Other Output VSS AC2
Pin Listing and Signal Descriptions Pin Name Pin Number Signal Buffer Type Direction Pin Name Pin Number Signal Buffer Type VSS B10 Power/Other VSS E26 Power/Other VSS B12 Power/Other VSS E4 Power/Other VSS B14 Power/Other VSS E7 Power/Other VSS B16 Power/Other VSS E9 Power/Other VSS B18 Power/Other VSS F10 Power/Other VSS B20 Power/Other VSS F12 Power/Other VSS B23 Power/Other VSS F14 Power/Other VSS B26 Power/Other VSS F16 Power/Other VSS B4 Power/
Pin Listing and Signal Descriptions Pin Name Pin Number Signal Buffer Type VSS N24 Power/Other VSS N3 Power/Other VSS N6 Power/Other VSS P2 Power/Other VSS P22 Power/Other VSS P25 Power/Other VSS P5 Power/Other VSS R1 Power/Other VSS R23 Power/Other VSS R26 Power/Other VSS R4 Power/Other VSS T21 Power/Other VSS T24 Power/Other VSS T3 Power/Other VSS T6 Power/Other VSS U2 Power/Other VSS U22 Power/Other VSS U25 Power/Other VSS U5 Power/Other VSS V
Pin Listing and Signal Descriptions Table 4-2. Numerical Pin Assignment (Sheet 1 of 12) Pin # A2 42 Pin Name THERMTRIP# Signal Buffer Type Asynch GTL+ A3 VSS Power/Other A4 VSS_SENSE Power/Other Direction Output Table 4-2.
Pin Listing and Signal Descriptions Table 4-2. Numerical Pin Assignment (Sheet 3 of 12) Pin # Pin Name D5 TDO D6 VSS D7 VCC D8 VSS D9 VCC D10 VSS D11 VCC D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 Signal Buffer Type TAP Direction Output Table 4-2.
Pin Listing and Signal Descriptions Table 4-2. Numerical Pin Assignment (Sheet 5 of 12) Pin # 44 Pin Name Signal Buffer Type Direction Table 4-2.
Pin Listing and Signal Descriptions Table 4-2. Numerical Pin Assignment (Sheet 7 of 12) Pin # Pin Name Signal Buffer Type Direction Table 4-2.
Pin Listing and Signal Descriptions Table 4-2. Numerical Pin Assignment (Sheet 9 of 12) Pin # 46 Pin Name Signal Buffer Type Y25 VSS Y26 D56# Source Synch AA1 VSS Power/Other Direction Power/Other Input/Output Table 4-2.
Pin Listing and Signal Descriptions Table 4-2. Numerical Pin Assignment (Sheet 11 of 12) Pin # Pin Name Signal Buffer Type Power/Other Direction AD1 BOOTSELECT AD2 VIDPWRGD AD3 VID5 AD4 VSS Power/Other AD5 BSEL1 Power/Other Output Output Table 4-2.
Pin Listing and Signal Descriptions Figure 4-1.
Pin Listing and Signal Descriptions Figure 4-2.
Pin Listing and Signal Descriptions 4.2 Alphabetical Signals Reference Table 4-3. Signal Description (Sheet 1 of 8) Name Type Description 236-byte A[35:3]# Input/ Output A[35:3]# (Address) define a physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the processor front side bus.
Pin Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 2 of 8) Name Type Description BINIT# (Bus Initialization) may be observed and driven by all processor front side bus agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation.
Pin Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 3 of 8) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor front side bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period.
Pin Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 4 of 8) Name Type Description DPSLP# Input DPSLP# when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state. In order to return to the Sleep State, DPSLP# must be deasserted and BCLK[1:0] must be running. DRDY# Input/ Output DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus.
Pin Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 5 of 8) Name IERR# Type Output Description IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor front side bus. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#.
Pin Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 6 of 8) Name Type Description MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor front side bus agents. MCERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options: MCERR# Input/ Output • Enabled or disabled. • Asserted, if configured, for internal errors along with IERR#.
Pin Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 7 of 8) Name RSP# SKTOCC# SLP# SMI# Type Input Description RSP# (Response Parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect to the appropriate pins of all processor front side bus agents.
Pin Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 8 of 8) Name THERMTRIP# Type Description Output In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond which permanent silicon damage may occur.
Pin Listing and Signal Descriptions 58 Mobile Intel® Pentium® 4 Processor Supporting Hyper-Threading Technology on 90-nm Process Technology Datasheet
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
Thermal Specifications and Design Considerations requirements, systems should be designed to the Fixed Mobile Solution (FMS) guidelines, even if a processor with a lower thermal dissipation is currently planned. In all cases, the Intel Thermal Monitor or Intel Thermal Monitor 2 feature must be enabled for the processor to remain within specification. Table 5-1. Processor Thermal Specifications Processor Number Core Frequency Thermal Design (GHz) Power (W) Minimum TC (°C) Maximum TC (°C) Notes 518 2.
Thermal Specifications and Design Considerations 5.2 Processor Thermal Features 5.2.1 Intel Thermal Monitor The Intel Thermal Monitor feature helps control the processor temperature by activating the TCC when the processor silicon reaches its maximum operating temperature. The TCC reduces processor power consumption as needed by modulating (starting and stopping) the internal processor core clocks.
Thermal Specifications and Design Considerations A processor enabled for the Intel Thermal Monitor 2 includes two operating points, each consisting of a specific operating frequency and voltage. The first operating point represents the normal operating condition for the processor. Under this condition, the core-frequency-to-FSB multiple utilized by the processor is that contained in the IA32_CR_FLEX_BRVID_SEL MSR and the VID is that specified in Table 2-8.
Thermal Specifications and Design Considerations 5.2.3 On-Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption. This mechanism is referred to as “On-Demand” mode and is distinct from the Intel Thermal Monitor feature. On-Demand mode is intended as a means to reduce system level power consumption. Systems utilizing the processor must not rely on software usage of this mechanism to limit the processor temperature.
Thermal Specifications and Design Considerations 5.2.5 THERMTRIP# Signal Pin Regardless of whether or not the Intel Thermal Monitor feature is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Table 4-3). At this point, the front side bus signal THERMTRIP# will go active and stay active as described in Table 4-3.
Thermal Specifications and Design Considerations 5. The series resistance, RT, is provided to allow for a more accurate measurement of the diode temperature. RT, as defined, includes the pins of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. RT can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term.
Thermal Specifications and Design Considerations 66 Mobile Intel® Pentium® 4 Processor Supporting Hyper-Threading Technology on 90-nm Process Technology Datasheet
Features 6 Features 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, please refer to Table 6-1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features 6.2.2 AutoHALT Power-Down State—State 2 AutoHALT is a low-power state entered when the processor executes the HALT instruction. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal mode or the AutoHALT Power-Down state.
Features Since the GTL+ signal pins receive power from the front side bus, these pins should not be driven (allowing the level to return to VCC) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the front side bus should be driven to the inactive state. BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched and can be serviced by software upon exit from the Stop-Grant state.
Features If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the reset sequence.
Features — If the target frequency is higher than the current frequency, Vcc is ramped up in incremental steps (+12.5 mV VID step) by placing a new value on the VID signals and the PLL then locks to the new frequency. Note that the top frequency for the processor can not be exceeded. — If the target frequency is lower than the current frequency, the PLL locks to the new frequency and then Vcc is ramped down in decremental steps (-12.5 mV VID step) by changing the target VID through the VID signals.
Features 72 Mobile Intel® Pentium® 4 Processor Supporting Hyper-Threading Technology on 90-nm Process Technology Datasheet
Debug Tools Specifications 7 Debug Tools Specifications Please refer to the appropriate platform design guidelines for information regarding debug tools specifications. The ITP700 Debug Port Design Guide is located on http://developer.intel.com. 7.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging processor systems.
Debug Tools Specifications 74 Mobile Intel® Pentium® 4 Processor Supporting Hyper-Threading Technology on 90-nm Process Technology Datasheet
