Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology* on 90 nm Process Technology Specification Update

38 Specification Update

Specification Changes

The Specification Changes listed in this section apply to the following documents:

• Mobile Intel

Pentium

4 Processor supporting Hyper-Threading Technology on 90-nm process

technology Datasheet

All Specification Changes will be incorporated into a future version of the appropriate Mobile Pentium 4

Processor supporting Hyper-Threading Technology on 90-nm process technology documentation.

Q1. Update to Processor T73: Deep Sleep PLL Lock Latency

Deep Sleep PLL Lock Latency for CPUID = 0xF41 has changed from 30 µs to 245 µs for the Max

specification.

Deep Sleep State—State 6

Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep Sleep

state is entered by asserting the DPSLP# pin while in the Sleep state. The DPSLP# pin must be de-

asserted to re-enter the Sleep state. A period of 245 microseconds (to allow for PLL stabilization) must

occur before the processor can be considered to be in the Sleep State. Once in the Sleep state, the SLP#

pin can be deasserted to re-enter the Stop-Grant state.