Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology* on 90 nm Process Technology Specification Update

Specification Update 37

Q63. A Write to an APIC Register Sometimes May Appear to Have Not Occurred

Problem: With respect to the retirement of instructions, stores to the uncacheable memory-based APIC register

space are handled in a non-synchronized way. For example if an instruction that masks the interrupt flag,

e.g. CLI, is executed soon after an uncacheable write to the Task Priority Register (TPR) that lowers the

APIC priority, the interrupt masking operation may take effect before the actual priority has been

lowered. This may cause interrupts whose priority is lower than the initial TPR, but higher than the final

TPR, to not be serviced until the interrupt enabled flag is finally set, i.e. by STI instruction. Interrupts

will remain pending and are not lost.

Implication: In this example the processor may allow interrupts to be accepted but may delay their service.

Workaround: This non-synchronization can be avoided by issuing an APIC register read after the APIC register write.

This will force the store to the APIC register before any subsequent instructions are executed. No

commercial operating system is known to be impacted by this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.