Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology* on 90 nm Process Technology Specification Update

R
36 Specification Update
Q60.
Front Side Bus Machine Checks May be Reported as a Result of On-Going
Transactions during Warm Reset
Problem: Processor Front Side Bus (FSB) protocol/signal integrity machine checks may be reported if the
transactions are initiated or in-progress during a warm reset. A warm reset is where the chipset asserts
RESET# when the system is running.
Implication: The processor may log FSB protocol/signal integrity machine checks if transactions are allowed to occur
during RESET# assertions.
Workaround: BIOS may clear FSB protocol/signal integrity machine checks for systems/chipsets which do not block
new transactions during RESET# assertions.
Status: For the steppings affected, see the Summary of Tables of Changes.
Q61.
At Core-to-Bus Ratios of 16:1 and above Defer Reply Transactions with Non-Zero
REQb Values May Cause a Front Side Bus Stall
Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken on the new
interrupt vector even if the mask bit is set.
Implication: An interrupt may immediately be generated with the new vector when a LVT entry is written, even if the
new LVT entry has the mask bit set. If there is no Interrupt Service Routine (ISR) set up for that vector
the system will GP fault. If the ISR does not do an End of Interrupt (EOI) the bit for the vector will be
left set in the in-service register and mask all interrupts at the same or lower priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if that vector was
programmed as masked. This ISR routine must do an EOI to clear any unexpected interrupts that may
occur. The ISR associated with the spurious vector does not generate an EOI, therefore the spurious
vector should not be used when writing the LVT.
Status: For the steppings affected, see the Summary Tables of Changes.
Q62.
The Processor May Issue Multiple Code Fetches to the Same Cache Line for
Systems with Slow Memory
Problem: Systems with long latencies on returning code fetch data from memory e.g. BIOS ROM, may cause the
processor to issue multiple fetches to the same cache line, once per each instruction executed.
Implication: This erratum may slow down system boot time. Intel has not observed a failure, as a result of this
erratum, in a commercially available system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.