Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology* on 90 nm Process Technology Specification Update

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Specification Update 35
Q57.
It Is Possible That Two Specific Invalid Opcodes May Cause Unexpected
Memory Accesses
Problem: A processor is expected to respond with an undefined opcode (#UD) fault when executing either opcode
0F 78 or a Grp 6 Opcode with bits 5:3 of the Mod/RM field set to 6, however the processor may respond
instead, with a load to an incorrect address.
Implication: This erratum may cause unpredictable system behavior or system hang.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary of Tables of Changes.
Q58.
At Core-to-Bus Ratios of 16:1 and above Defer Reply Transactions with Non-
Zero REQb Values May Cause a Front Side Bus Stall
Problem: Problem: Certain processors are likely to hang the Front Side Bus (FSB) if the following conditions are
met:
1. A Defer Reply transaction has a REQb[2:0] value of either 010b, 011b, 100b, 110b, or 111b, and
2. The operating bus ratio is 16:1 or higher
When these conditions are met, the processor may incorrectly and indefinitely assert a snoop stall for
the Defer Reply transaction. Such an event will block further progress on the FSB.
Implication: If this erratum occurs, the system may hang. Intel has not observed this erratum with any commercially
available system.
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes.
Q59.
The Processor May Issue Front Side Bus Transactions up to 6 Clocks after
RESET# is Asserted
Problem: The processor may issue transactions beyond the documented 3 Front Side Bus (FSB) clocks and up to 6
FSB clocks after RESET# is asserted in the case of a warm reset. A warm reset is where the chipset
asserts RESET# when the system is running.
Implication: The processor may issue transactions up to 6 FSB clocks after RESET# is asserted.
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes.